56F8357 View Datasheet(PDF) - Freescale Semiconductor
Part Name
Description
Manufacturer
56F8357 Datasheet PDF : 177 Pages
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Signal Pins
Table 2-2 Signal and Package Information for the 160-Pin LQFP and MBGA
Signal
Name
Pin
No.
Ball No.
Type
State
During
Reset
Signal Description
XTAL
93
K12
Input/ Chip-driven Crystal Oscillator Output — This output connects the internal
Output
crystal oscillator output to an external crystal.
If an external clock is used, XTAL must be used as the input
and EXTAL connected to GND.
CLKO
The input clock can be selected to provide the clock directly to
the core. This input clock can also be selected as the input
clock for the on-chip PLL.
3
D3
Output
In reset, Clock Output — This pin outputs a buffered clock signal.
output is Using the SIM CLKO Select Register (SIM_CLKOSR), this pin
disabled can be programmed as any of the following: disabled,
CLK_MSTR (system clock), IPBus clock, oscillator output,
prescaler clock and postscaler clock. Other signals are also
available for test purposes.
See Part 6.5.7 for details.
A0
154
C3
Output
In reset, Address Bus — A0 - A5 specify six of the address lines for
output is external program or data memory accesses.
disabled,
pull-up is Depending upon the state of the DRV bit in the EMI bus control
enabled register (BCR), A0–A5 and EMI control signals are tri-stated
when the external bus is inactive.
Most designs will want to change the DRV state to DRV = 1
instead of using the default setting.
(GPIOA8)
A1
10
(GPIOA9)
A2
11
(GPIOA10)
A3
12
(GPIOA11)
A4
13
(GPIOA12)
A5
14
(GPIOA13)
Input/
Output
E3
E4
F2
F1
F3
Port A GPIO — These six GPIO pins can be individually
programmed as input or output pins.
After reset, the default state is Address Bus.
To deactivate the internal pull-up resistor, clear the appropriate
GPIO bit in the GPIOA_PUR register.
Example: GPIOA8, clear bit 8 in the GPIOA_PUR register.
56F8357 Technical Data, Rev. 15
Freescale Semiconductor
21
Preliminary
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