56F8357 View Datasheet(PDF) - Freescale Semiconductor
Part Name
Description
Manufacturer
56F8357 Datasheet PDF : 177 Pages
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Table of Contents
Part 1: Overview. . . . . . . . . . . . . . . . . . . . . . . 6
1.1. 56F8357/56F8157 Features . . . . . . . . . . . . . 6
1.2. Device Description . . . . . . . . . . . . . . . . . . . . 8
1.3. Award-Winning Development Environmen . 10
1.4. Architecture Block Diagram . . . . . . . . . . . . . 11
1.5. Product Documentation . . . . . . . . . . . . . . . 15
1.6. Data Sheet Conventions . . . . . . . . . . . . . . 15
Part 2: Signal/Connection Descriptions . . . 16
2.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.2. Signal Pins . . . . . . . . . . . . . . . . . . . . . . . . . 19
Part 3: On-Chip Clock Synthesis (OCCS) . 39
3.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.2. External Clock Operation . . . . . . . . . . . . . . 39
3.3. Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Part 4: Memory Map . . . . . . . . . . . . . . . . . . . 41
4.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 41
4.2. Program Map . . . . . . . . . . . . . . . . . . . . . . . 42
4.3. Interrupt Vector Table . . . . . . . . . . . . . . . . . 43
4.4. Data Map . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
4.5. Flash Memory Map . . . . . . . . . . . . . . . . . . . 47
4.6. EOnCE Memory Map . . . . . . . . . . . . . . . . . 48
4.7. Peripheral Memory Mapped Registers . . . . 49
4.8. Factory Programmed Memory. . . . . . . . . . . 76
Part 5: Interrupt Controller (ITCN) . . . . . . . . 76
5.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 76
5.2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
5.3. Functional Description . . . . . . . . . . . . . . . . . 76
5.4. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . 78
5.5. Operating Modes . . . . . . . . . . . . . . . . . . . . . 78
5.6. Register Descriptions . . . . . . . . . . . . . . . . . 79
5.7. Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Part 6: System Integration Module (SIM) . 106
6.1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . 106
6.2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . 106
6.3. Operating Modes . . . . . . . . . . . . . . . . . . . . 107
6.4. Operating Mode Register . . . . . . . . . . . . . 107
6.5. Register Descriptions . . . . . . . . . . . . . . . . 108
6.6. Clock Generation Overview . . . . . . . . . . . 121
6.7. Power Down Modes Overview . . . . . . . . . 121
6.8. Stop and Wait Mode Disable Function . . . 122
6.9. Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Part 7: Security Features . . . . . . . . . . . . . . 123
7.1. Operation with Security Enabled . . . . . . . 123
7.2. Flash Access Blocking Mechanisms . . . . 124
Part 8: General Purpose Input/Output
(GPIO) . . . . . . . . . . . . . . . . . . . . . . . 126
8.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . 126
8.2. Memory Maps . . . . . . . . . . . . . . . . . . . . . . . 126
8.3. Configuration. . . . . . . . . . . . . . . . . . . . . . . 126
Part 9: Joint Test Action Group (JTAG) . . 131
9.1. JTAG Information . . . . . . . . . . . . . . . . . . . 131
Part 10: Specifications . . . . . . . . . . . . . . . 131
10.1. General Characteristics. . . . . . . . . . . . . . 131
10.2. DC Electrical Characteristics. . . . . . . . . . 135
10.3. AC Electrical Characteristics . . . . . . . . . . 139
10.4. Flash Memory Characteristics . . . . . . . . . 139
10.5. External Clock Operation Timing . . . . . . 140
10.6. Phase Locked Loop Timing. . . . . . . . . . . 140
10.7. Crystal Oscillator Timing . . . . . . . . . . . . . 141
10.8. External Memory Interface Timing . . . . . 141
10.9. Reset, Stop, Wait, Mode Select, and
Interrupt Timing . . . . . . . . . . . . . . 144
10.10. Serial Peripheral Interface (SPI) Timing . 146
10.11. Quad Timer Timing . . . . . . . . . . . . . . . . 150
10.12. Quadrature Decoder Timing . . . . . . . . . . 150
10.13. Serial Communication Interface
(SCI) Timing . . . . . . . . . . . . . . . . 151
10.14. Controller Area Network (CAN) Timing . 152
10.15. JTAG Timing . . . . . . . . . . . . . . . . . . . . . 152
10.16. Analog-to-Digital Converter
(ADC) Parameters . . . . . . . . . . . 154
10.17. Equivalent Circuit for ADC Inputs . . . . . 157
10.18. Power Consumption . . . . . . . . . . . . . . . 157
Part 11: Packaging . . . . . . . . . . . . . . . . . . 159
11.1. 56F8357 Package and Pin-Out
Information . . . . . . . . . . . . . . . . . 159
11.2. 56F8157 Package and Pin-Out
Information . . . . . . . . . . . . . . . . . 166
Part 12: Design Considerations . . . . . . . . 170
12.1. Thermal Design Considerations . . . . . . . 170
12.2. Electrical Design Considerations . . . . . . 171
12.3. Power Distribution and I/O Ring
Implementation . . . . . . . . . . . . . . 172
Part 13: Ordering Information . . . . . . . . . 173
56F8357 Technical Data, Rev. 15
Freescale Semiconductor
5
Preliminary
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