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56F8357 View Datasheet(PDF) - Freescale Semiconductor

Part Name
Description
Manufacturer
56F8357
Freescale
Freescale Semiconductor Freescale
56F8357 Datasheet PDF : 177 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
Part 1 Overview
1.1 56F8357/56F8157 Features
1.1.1 Core
• Efficient 16-bit 56800E family controller engine with dual Harvard architecture
• Up to 60 Million Instructions Per Second (MIPS) at 60 MHz core frequency
• Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC)
• Four 36-bit accumulators, including extension bits
• Arithmetic and logic multi-bit shifter
• Parallel instruction set with unique DSP addressing modes
• Hardware DO and REP loops
• Three internal address buses
• Four internal data buses
• Instruction set supports both DSP and controller functions
• Controller-style addressing modes and instructions for compact code
• Efficient C compiler and local variable support
• Software subroutine and interrupt stack with depth limited only by memory
• JTAG/EOnCE debug programming interface
1.1.2 Differences Between Devices
Table 1-1 outlines the key differences between the 56F8357 and 56F8157 devices.
Table 1-1 Device Differences
Feature
56F8357
Guaranteed Speed
Program RAM
Data Flash
60MHz/60 MIPS
4KB
8KB
PWM
2x6
CAN
1
Quad Timer
Quadrature Decoder
4
2x4
Temperature Sensor
1
Dedicated GPIO
56F8157
40MHz/40 MIPS
Not Available
Not Available
1x6
Not Available
2
1x4
Not Available
7
56F8357 Technical Data, Rev. 15
6
Freescale Semiconductor
Preliminary

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