56F8357 View Datasheet(PDF) - Freescale Semiconductor

Part Name

Description

Manufacturer

56F8357

16-bit Digital Signal Controllers

Freescale Semiconductor 

• Two Serial Communication Interfaces (SCIs), each with two pins (or four additional GPIO lines)

• Two Serial Peripheral Interfaces (SPIs). both with configurable 4-pin port (or eight additional GPIO lines);

SPI1 can also be used as Quadrature Decoder 1 or Quad Timer B

— In the 56F8357, SPI1 can also be used as Quadrature Decoder 1 or Quad Timer B

— In the 56F8157, SPI1 can alternately be used only as GPIO

• Computer Operating Properly (COP) / Watchdog timer

• Two dedicated external interrupt pins

• Up to 76 General Purpose I/O (GPIO) pins

• External reset input pin for hardware reset

• External reset output pin for system reset

• Integrated Low-Voltage Interrupt Module

• JTAG/Enhanced On-Chip Emulation (OnCE™) for unobtrusive, processor speed-independent debugging

• Software-programmable, Phase Lock Loop (PLL)-based frequency synthesizer for the core clock

1.1.5 Energy Information

• Fabricated in high-density CMOS with 5V-tolerant, TTL-compatible digital inputs

• On-board 3.3V down to 2.6V voltage regulator for powering internal logic and memories; can be disabled

• On-chip regulators for digital and analog circuitry to lower cost and reduce noise

• Wait and Stop modes available

• ADC smart power management

• Each peripheral can be individually disabled to save power

1.2 Device Description

The 56F8357 and 56F8157 are members of the 56800E core-based family of controllers. Each combines,

on a single chip, the processing power of a Digital Signal Processor (DSP) and the functionality of a

microcontroller with a flexible set of peripherals to create an extremely cost-effective solution. Because

of its low cost, configuration flexibility, and compact program code, the 56F8357 and 56F8157 are

well-suited for many applications. The device includes many peripherals that are especially useful for

motion control, smart appliances, steppers, encoders, tachometers, limit switches, power supply and

control, automotive control (56F8357 only), engine management, noise suppression, remote utility

metering, industrial control for power, lighting, and automation applications.

The 56800E core is based on a Harvard-style architecture consisting of three execution units operating in

parallel, allowing as many as six operations per instruction cycle. The MCU-style programming model and

optimized instruction set allow straightforward generation of efficient, compact DSP and control code.

The instruction set is also highly efficient for C/C++ Compilers to enable rapid development of optimized

control applications.

The 56F8357 and 56F8157 support program execution from internal or external memories. Two data

operands can be accessed from the on-chip data RAM per instruction cycle. These devices also provide

two external dedicated interrupt lines and up to 76 General Purpose Input/Output (GPIO) lines, depending

on peripheral configuration.

56F8357 Technical Data, Rev. 15

8

Freescale Semiconductor

Preliminary

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