DSP56852VFE View Datasheet(PDF) - Freescale Semiconductor
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DSP56852VFE Datasheet PDF : 48 Pages
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Table 4-4 DC Electrical Characteristics (Continued)
Operating Conditions: VSS = VSSIO = VSSA = 0V, VDD = 1.62-1.98V, VDDIO = VDDA = 3.0–3.6V, TA = –40° to +120°C, CL < 50pF, fop = 120MHz
Characteristic
Symbol
Min
Typ
Max
Unit
VDD supply current (Core logic, memories, peripherals)
IDD4
Run 1
Deep Stop2
Light Stop3
—
55
70
mA
—
0.02
2.5
mA
—
3.4
8
mA
VDDIO supply current (I/O circuity)
Run5
Deep Stop2
IDDIO
—
40
50
mA
—
0
300
μA
VDDA supply current (analog circuity)
Deep Stop2
IDDA
—
60
120
μA
Low Voltage Interrupt6
VEI
—
2.5
2.85
V
Low Voltage Interrupt Recovery Hysteresis
VEIH
—
50
—
mV
Power on Reset7
POR
—
1.5
2.0
V
Note: Run (operating) IDD measured using external square wave clock source (fosc = 4MHz) into XTAL. All inputs 0.2V from rail;
no DC loads; outputs unloaded. All ports configured as inputs; measured with all modules enabled. PLL set to 240MHz out.
1. Running Core, performing 50% NOP and 50% FIR. Clock at 120 MHz.
2. Deep Stop Mode - Operation frequency = 4 MHz, PLL set to 4 MHz, crystal oscillator.
3. Light Stop Mode - Operation frequency = 120 MHz, PLL set to 240 MHz, crystal oscillator.
4. IDD includes current for core logic, internal memories, and all internal peripheral logic circuitry.
5. Running core and performing external memory access. Clock at 120 MHz.
6. When VDD drops below VEI max value, an interrupt is generated.
7. Power-on reset occurs whenever the digital supply drops below 1.8V. While power is ramping up, this signal remains active
as long as the internal 2.5V is below 1.8V, no matter how long the ramp up rate is. The internally regulated voltage is typically
100mV less than VDD during ramp up until 2.5V is reached, at which time it self-regulates.
56852 Technical Data, Rev. 8
18
Freescale Semiconductor
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