DSP56852 View Datasheet(PDF) - Freescale Semiconductor
Part Name
Description
Manufacturer
DSP56852 Datasheet PDF : 48 Pages
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DSP56852 General Description
• 120 MIPS at 120MHz
• 6K x 16-bit Program SRAM
• 4K x 16-bit Data SRAM
• 1K x 16-bit Boot ROM
• 21 External Memory Address lines, 16 data lines and
four chip selects
• One (1) Serial Port Interface (SPI) or one (1) Improved
Synchronous Serial Interface (ISSI)
• One (1) Serial Communication Interface (SCI)
• Interrupt Controller
• General Purpose 16-bit Quad Timer
• JTAG/Enhanced On-Chip Emulation (OnCE™) for
unobtrusive, real-time debugging
• Computer Operating Properly (COP)/Watchdog Timer
• 81-pin MAPBGA package
• Up to 11 GPIO
Memory
Program Memory
6144 x 16 SRAM
Boot ROM
1024 x 16 ROM
Data Memory
4096 x 16 SRAM
6
JTAG/
Enhanced
OnCE
VDDIO
6
VDD VSSIO VSS VDDA VSSA
3
63
16-Bit
56800E Core
Program Controller
and
Hardware Looping Unit
Address
Generation Unit
Data ALU
16 x 16 + 36 → 36-Bit MAC
Three 16-bit Input Registers
Four 36-bit Accumulators
Bit
Manipulation
Unit
PAB
PDB
CDBR
CDBW
XDB2
XAB1
XAB2
PAB
PDB
CDBR
CDBW
R/W Control
System
Bus
Control
A0-16
A17-18 muxed (timer pins)
A19 muxed (CS3)
D0-D12[12:0]
D13-15 muxed (Mode A,B,C)
WR Enable
RD Enable
CS[2:0] muxed (GPIOA)
System
Address
Decoder
System
Device
IPBus Bridge (IPBB)
Peripheral
Address
Decoder
Decoding
Peripherals
External Address
Bus Switch
External Data
Bus Switch
External Bus
Interface Unit
Bus Control
Peripheral
Device
Selects
RW
IPAB
Control
IPWDB
IPRDB
SCI or
GPIOE
1 Quad
Timer
or A17,
A18
SSI or
SPI or
GPIOC
COP/
Watch-
dog
Interrupt
Controller
Clock
resets
P
O
R
System
Integration
Module
PLL
Clock
O
S
Generator C
2
2
6
IRQA
IRQB
RESET 3
CLKO
MODE muxed (A20)
muxed (D13-15)
56852 Block Diagram
XTAL
EXTAL
56852 Technical Data, Rev. 8
Freescale Semiconductor
3
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