DSP56853 View Datasheet(PDF) - Freescale Semiconductor

Part Name

Description

Manufacturer

DSP56853

16-bit Digital Signal Controllers

Freescale Semiconductor 

Introduction

Table 3-1. 56853 Signal and Package Information for the 128-pin LQFP (Continued)

Pin No.

54

Signal Name

TCK

52

TDI

51

TDO

53

TMS

Type

Input

Input

Output (Z)

Input

Description

Test Clock Input (TCK)—This input pin provides a gated clock to

synchronize the test logic and to shift serial data to the

JTAG/Enhanced OnCE port. The pin is connected internally to a

pull-down resistor.

Test Data Input (TDI)—This input pin provides a serial input data

stream to the JTAG/Enhanced OnCE port. It is sampled on the rising

edge of TCK and has an on-chip pull-up resistor.

Test Data Output (TDO)—This tri-statable output pin provides a

serial output data stream from the JTAG/Enhanced OnCE port. It is

driven in the Shift-IR and Shift-DR controller states, and changes on

the falling edge of TCK.

Test Mode Select Input (TMS)—This input pin is used to sequence

the JTAG TAP controller’s state machine. It is sampled on the rising

edge of TCK and has an on-chip pull-up resistor.

50

TRST

Input

Note: Always tie the TMS pin to VDD through a 2.2K resistor.

Test Reset (TRST)—As an input, a low signal on this pin provides a

reset signal to the JTAG TAP controller. To ensure complete

hardware reset, TRST should be asserted whenever RESET is

asserted. The only exception occurs in a debugging environment,

since the Enhanced OnCE/JTAG module is under the control of the

debugger. In this case it is not necessary to assert TRST when

asserting RESET. Outside of a debugging environment RESET

should be permanently asserted by grounding the signal, thus

disabling the Enhanced OnCE/JTAG module on the controller.

Note: For normal operation, connect TRST directly to VSS. If the design

is to be used in a debugging environment, TRST may be tied to VSS through

a 1K resistor.

49

DE

Input/Output Debug Event (DE)—This is an open-drain, bidirectional, active low

signal. As an input, it is a means of entering debug mode of operation

from an external command controller. As an output, it is a means of

acknowledging that the chip has entered debug mode.

This pin is connected internally to a weak pull-up resistor.

56853 Technical Data, Rev. 6

Freescale Semiconductor

21

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