DSP56853 View Datasheet(PDF) - Freescale Semiconductor

Part Name

Description

Manufacturer

DSP56853

16-bit Digital Signal Controllers

Freescale Semiconductor 

56853 Description

• Watchdog Timer

• JTAG/Enhanced On-Chip Emulation (OnCE) for unobtrusive, real-time debugging

• Six (6) independent channels of DMA

• 8-bit Parallel Host Interface*

• Time-of-Day (TOD)

• 128 LQFP package

• Up to 41 GPIO

* Each peripheral I/O can be used alternately as a General Purpose I/O if not needed

1.1.4 Energy Information

• Fabricated in high-density CMOS with 3.3V, TTL-compatible digital inputs

• Wait and Stop modes available

1.2 56853 Description

The 56853 is a member of the 56800E core-based family of controllers. It combines, on a single chip, the

processing power of a Digital Signal Processor (DSP) and the functionality of a microcontroller with a

flexible set of peripherals to create an extremely cost-effective solution. Because of its low cost,

configuration flexibility, and compact program code, the 56853 is well-suited for many applications. The

56853 includes many peripherals that are especially useful for low-end Internet appliance applications

and low-end client applications such as telephony; portable devices; Internet audio and point-of-sale

systems, such as noise suppression; ID tag readers; sonic/subsonic detectors; security access devices;

remote metering; sonic alarms.

The 56800E core is based on a Harvard-style architecture consisting of three execution units operating in

parallel, allowing as many as six operations per instruction cycle. The microprocessor-style programming

model and optimized instruction set allow straightforward generation of efficient, compact DSP and

control code. The instruction set is also highly efficient for C Compilers, enabling rapid development of

optimized control applications.

The 56853 supports program execution from either internal or external memories. Two data operands can

be accessed from the on-chip Data RAM per instruction cycle. The 56853 also provides two external

dedicated interrupt lines, and up to 41 General Purpose Input/Output (GPIO) lines, depending on

peripheral configuration.

The 56853 controller includes 12K words of Program RAM, 4K words of Data RAM, and 1K words of

Boot ROM. It also supports program execution from external memory. The 56800 core can access two data

operands from the on-chip Data RAM per instruction cycle.

This controller also provides a full set of standard programmable peripherals that include an 8-bit parallel

Host Interface, Enhanced Synchronous Serial Interface (ESSI), one Serial Peripheral Interface (SPI), the

option to select a second SPI or two Serial Communications Interfaces (SCIs), and Quad Timer. The Host

Interface, ESSI, SPI, SCI, four chip selects and quad timer can be used as General Purpose Input/Outputs

(GPIOs) if its primary function is not required.

56853 Technical Data, Rev. 6

Freescale Semiconductor

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