MK74CB163RTR View Datasheet(PDF) - Integrated Circuit Systems
Part Name
Description
Manufacturer
MK74CB163RTR Datasheet PDF : 5 Pages
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PRELIMINARY INFORMATION
MK74CB163
1 to 16 PECL to CMOS Buffalo™ Clock Driver
Pin Assignment
Suggested Layout
OE0 1
Q0 2
Q1 3
Q2 4
VDD 5
VDD 6
Q3 7
Q4 8
GND 9
GND 10
Q5 11
Q6 12
Q7 13
PECLIN 14
28 OE1
27 Q15
26 Q14
25 Q13
24 VDD
23 VDD
22 Q12
21 Q11
20 GND
19 GND
18 Q10
17 Q9
16 Q8
15 PECLIN
V
0.1µF
G
V
0.1µF
G
For simplicity, 33 Ω series termination resistors are not
shown for the outputs, but should be placed as close to the
device as possible. It is most critical to have the 0.1µF
decoupling capacitors closest.
Pin Descriptions
V = connect to VDD G = connect to GND
Number
Name
Type Description
1
OE0
I Output Enable. Tri-states Q0 to Q5 clock outputs when this input is low. Internal pull-up.
2, 3, 4 Q0, Q1, Q2
O Clock outputs.
5, 6
VDD
P Power supply. Connect to +3.3V.
7, 8
Q3, Q4
O Clock outputs.
9, 10
GND
P Connect to ground.
11, 12, 13 Q5, Q6, Q7
O Clock outputs.
14
PECLIN
I Complementary PECL input.
15
PECLIN
I True PECL input.
16, 17, 18 Q8, Q9, Q10
O Clock outputs.
19, 20
GND
P Connect to ground.
21, 22 Q11, Q12
O Clock outputs.
23, 24
VDD
P Power supply. Connect to +3.3V.
25, 26, 27 Q13, Q14, Q15 O Clock outputs.
28
OE1
I Output Enable. Tri-states Q6 to Q15 clock outputs when this input is low. Internal pull-up.
Type: I = Input, O = output, P = power supply connection
MDS 74CB163 A
2
Revision 112399
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose •CA•95126• (408)295-9800tel • www.icst.com
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