GS8322Z72C View Datasheet(PDF) - Giga Semiconductor

Part Name

Description

Manufacturer

GS8322Z72C

36Mb Pipelined and Flow Through Synchronous NBT SRAM

Giga Semiconductor 

Product Preview

GS8322Z18(B/C)/GS8322Z36(B/C)/GS8322Z72(C)

119 and 209 BGA 36Mb Pipelined and Flow Through 250 MHz–133 MHz

Commercial Temp

Industrial Temp

Synchronous NBT SRAM

2.5 V or 3.3 V VDD

2.5 V or 3.3 V I/O

Features

• NBT (No Bus Turn Around) functionality allows zero wait

Read-Write-Read bus utilization; fully pin-compatible with

both pipelined and flow through NtRAM™, NoBL™ and

ZBT™ SRAMs

• 2.5 V or 3.3 V +10%/–5% core power supply

• 2.5 V or 3.3 V I/O supply

• User-configurable Pipeline and Flow Through mode

• ZQ mode pin for user-selectable high/low output drive

• IEEE 1149.1 JTAG-compatible Boundary Scan

• On-chip write parity checking; even or odd selectable

• On-chip parity encoding and error detection

• LBO pin for Linear or Interleave Burst mode

• Pin-compatible with 2Mb, 4Mb, 8Mb, and 16Mb devices

• Byte write operation (9-bit Bytes)

• 3 chip enable signals for easy depth expansion

• ZZ Pin for automatic power-down

• JEDEC-standard 119- or 209-Bump BGA package

input clock. Burst order control (LBO) must be tied to a power

rail for proper operation. Asynchronous inputs include the

Sleep mode enable (ZZ) and Output Enable. Output Enable can

be used to override the synchronous control of the output

drivers and turn the RAM's output drivers off at any time.

Write cycles are internally self-timed and initiated by the rising

edge of the clock input. This feature eliminates complex off-

chip write pulse generation required by asynchronous SRAMs

and simplifies input signal timing.

The GS8322Z18/36/72 may be configured by the user to

operate in Pipeline or Flow Through mode. Operating as a

pipelined synchronous device, in addition to the rising-edge-

triggered registers that capture input signals, the device

incorporates a rising edge triggered output register. For read

cycles, pipelined SRAM output data is temporarily stored by

the edge-triggered output register during the access cycle and

then released to the output drivers at the next rising edge of

clock.

Pipeline

3-1-1-1

3.3 V

2.5 V

Flow

Through

2-1-1-1

3.3 V

2.5 V

tKQ

tCycle

Curr (x18)

Curr (x36)

Curr (x72)

Curr (x18)

Curr (x36)

Curr (x72)

tKQ

tCycle

Curr (x18)

Curr (x36)

Curr (x72)

Curr (x18)

Curr (x36)

Curr (x72)

-250 -225 -200 -166 -150 -133 Unit

2.3 2.5 3.0 3.5 3.8 4.0 ns

4.0 4.4 5.0 6.0 6.6 7.5 ns

365 335 305 265 245 215 mA

560 510 460 400 370 330 mA

660 600 540 460 430 380 mA

360 330 305 260 240 215 mA

550 500 460 390 360 330 mA

640 590 530 450 420 370 mA

6.0 6.5 7.5 8.5 10 11 ns

7.0 7.5 8.5 10 10 15 ns

235 230 210 200 195 150 mA

300 300 270 270 270 200 mA

350 350 300 300 300 220 mA

235 230 210 200 195 145 mA

300 300 270 270 270 190 mA

340 340 300 300 300 220 mA

The GS8322Z18/36/72 is implemented with GSI's high

performance CMOS technology and is available in a JEDEC-

standard 119-bump or 209-bump BGA package.

Functional Description

The GS8322Z18/36/72 is a 36Mbit Synchronous Static

SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or

other pipelined read/double late write or flow through read/

single late write SRAMs, allow utilization of all available bus

bandwidth by eliminating the need to insert deselect cycles

when the device is switched from read to write cycles.

Because it is a synchronous device, address, data inputs, and

read/write control inputs are captured on the rising edge of the

Rev: 1.00 10/2001

1/42

© 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc.

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