GS8322Z72C View Datasheet(PDF) - Giga Semiconductor

Part Name

Description

Manufacturer

GS8322Z72C

36Mb Pipelined and Flow Through Synchronous NBT SRAM

Giga Semiconductor 

Product Preview

GS8322Z18(B/C)/GS8322Z36(B/C)/GS8322Z72(C)

GS8322Z18/36/72 209-Bump BGA Pin Description

Pin Location

W6, V6

W7, W5, V9, V8, V7, V5, V4, V3, U8, U6, U4,

A3, A5, A7, B7, A9, U7

B5

C7

L11, M11, N11, P11, L10, M10, N10, P10, R10

A10, B10, C10, D10, A11, B11, C11, D11, E11

J1, H1, G1, F1, J2, H2, G2, F2, E2

W2, V2, U2, T2, W1, V1, U1, T1, R1

W10, V10, U10, T10, W11, V11, U11, T11, R11

J11, H11, G11, F11, J10, H10, G10, F10, E10

A2, B2, C2, D2, A1, B1, C1, D1, E1

L1, M1, N1, P1, L2, M2, N2, P2, R2

L11, M11, N11, P11, L10, M10, N10, P10, R10

A10, B10, C10, D10, A11, B11, C11, D11, E11

J1, H1, G1, F1, J2, H2, G2, F2, E2

W2, V2, U2, T2, W1, V1, U1, T1, R1

L11, M11, N11, P11, L10, M10, N10, P10, R10

J1, H1, G1, F1, J2, H2, G2, F2, E2

C9, B8

Symbol

A0, A1

An

A19

A20

DQA1–DQA9

DQB1–DQB9

DQC1–DQC9

DQD1–DQD9

DQE1–DQE9

DQF1–DQF9

DQG1–DQG9

DQH1–DQH9

DQA1–DQA9

DQB1–DQB9

DQC1–DQC9

DQD1–DQD9

DQA1–DQA9

DQB1–DQB9

BA, BB

Type

I

I

I

I

I/O

I/O

I/O

I

B3, C4

BC,BD

I

C8, B9, B4, C3

BE, BF, BG,BH I

B5

NC

—

C7

NC

—

W10, V10, U10, T10, W11, V11, U11, T11, R11

J11, H11, G11, F11, J10, H10, G10, F10, E10

A2, B2, C2, D2, A1, B1, C1, D1, E1

NC

—

L1, M1, N1, P1, L2, M2, N2, P2, R2, C8, B9,

B4, C3

B3, C4

NC

—

C5, D4, D5, D7, D8, K1, K2, K4, K8, K9, K10,

K11, T4, T5, T7, T8, U3, U5, U9

NC

—

K3

CK

I

C6

E1

I

A8

E3

I

A4

E2

I

D6

G

I

A6

ADV

I

Description

Address field LSBs and Address Counter Preset Inputs.

Address Inputs

Address Inputs (x36/x18 Versions)

Address Inputs (x18 Version)

Data Input and Output pins (x72 Version)

Data Input and Output pins (x36 Version)

Data Input and Output pins (x18 Version)

Byte Write Enable for DQA, DQB I/Os; active low

Byte Write Enable for DQC, DQD I/Os; active low

(x72/x36 Versions)

Byte Write Enable for DQE, DQF, DQG, DQH I/Os; active low

(x72 Version)

No Connect (x72 Version)

No Connect (x72/x36 Versions)

No Connect (x36/x18 Versions)

No Connect (x18 Version)

No Connect

Clock Input Signal; active high

Chip Enable; active low

Chip Enable; active low

Chip Enable; active high

Output Enable; active low

Burst address counter advance enable

Rev: 1.00 10/2001

5/42

© 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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