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73S8009CN View Datasheet(PDF) - Teridian Semiconductor Corporation

Part Name
Description
Manufacturer
73S8009CN
TERIDIAN
Teridian Semiconductor Corporation TERIDIAN
73S8009CN Datasheet PDF : 30 Pages
First Prev 21 22 23 24 25 26 27 28 29 30
73S8009CN Data Sheet
DS_8009CN_026
3.9 I/O Circuitry and Timing
The states of the I/O, AUX1, and AUX2 pins are low after power on reset and they are in high when the
activation sequencer turns on the I/O reception state. See the Activation and De-activation Sequence
section for more details on when the I/O reception is enabled. The states of I/OUC, AUX1UC, and
AUX2UC are high after power on reset.
Within a card session and when the I/O reception state is turned on, the first I/O line on which a falling
edge is detected becomes the input I/O line and the other becomes the output I/O line. When the input
I/O line rising edge is detected, then both I/O lines return to their neutral state. Figure 6 shows the state
diagram of how the I/O and I/OUC lines are managed to become input or output.
Neutral
State
No
I/O
reception
Yes
I/O
&
not I/OUC
No
Yes
No
I/OUC
&
not I/O
Yes
I/OUC
in
I/OICC
in
No
No
I/OUC
I/O
yes
yes
Figure 9: I/O and I/OUC State Diagram
22
Rev. 1.4

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