74LCXZ16244MEAX(2000) View Datasheet(PDF) - Fairchild Semiconductor

Part Name

Description

Manufacturer

74LCXZ16244MEAX
(Rev.:2000)

Low Voltage 16-Bit Bidirectional Transceiver with 5V Tolerant Inputs and Outputs

Fairchild Semiconductor 

September 2000

Revised September 2000

74LCXZ16244

Low Voltage 16-Bit Buffer/Line Driver

with 5V Tolerant Inputs and Outputs

General Description

The LCXZ16244 contains sixteen non-inverting buffers

with 3-STATE outputs designed to be employed as a mem-

ory and address driver, clock driver, or bus oriented trans-

mitter/receiver. The device is nibble controlled. Each nibble

has separate 3-STATE control inputs which can be shorted

together for full 16-bit operation.

When VCC is between 0 and 1.5V, the LCXZ12644 is in the

high impedance state during power up or power down. This

places the outputs in high impedance (Z) state preventing

intermittent low impedance loading or glitching in bus ori-

ented applications.

The LCXZ16244 is designed for low voltage (2.7V or 3.3V)

VCC applications with capability of interfacing to a 5V signal

environment.

The LCXZ16244 is fabricated with an advanced CMOS

technology to achieve high speed operation while maintain-

ing CMOS low power dissipation.

Features

s 5V tolerant inputs and outputs

s Guaranteed power up/down high impedance

s Supports live insertion/withdrawal

s 2.7V–3.6V VCC specifications provided

s 4.5 ns tPD max (VCC = 3.0V), 20 µA ICC max

s ±24 mA output drive (VCC = 3.0V)

s Implements patented noise/EMI reduction circuitry

s Latch-up performance exceeds 500 mA

s ESD performance:

Human body model > 2000V

Machine model > 200V

Ordering Code:

Order Number Package Number

Package Description

74LCXZ16244MEA

MS48A

48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300 Wide

74LCXZ16244MTD

MTD48

48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram

Logic Symbol

Pin Descriptions

Pin Names

OEn

I0–I15

O0–O15

Description

Output Enable Input (Active LOW)

Inputs

Outputs

© 2000 Fairchild Semiconductor Corporation DS500252

www.fairchildsemi.com

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