VSC9680 View Datasheet(PDF) - Vitesse Semiconductor
Part Name
Description
Manufacturer
VSC9680 Datasheet PDF : 2 Pages
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2048 Channel HDLC/ATM Controller
TimeStream
Product
Family
VSC9680
Product Brief
VSC9680 Block Diagram
Features:
• 2048 full duplex HDLC channels
• 3 full duplex DS3 or HSSI
channels
• 16 HDSL and 8 ADSL channels
• 28 T1 or 32 E1 channels
• Up to 84 T1 or 63 E1 channels
via a proprietary interface to the
VSC967x Framer product family
• Combined throughput up to
135 Mbps
• Delineates HDLC packets or ATM
cells per logical channel
• Flexible and powerful mapping of
DS0 physical to logical channels
• HDLC flag insertion, bit stuffing,
CRC-16/32 generation for each
transmit channel
• HDLC flag detection, bit de-
stuffing and CRC-16/32 calcula-
tion for each receive channel
• Detects a valid ATM cell by
framing to the HEC in the receive
direction, and inserts an HEC
value for each ATM cell in the
transmit direction.
• 2048 channel scatter gather DMA
engine transfers packets to and
from host memory using a flexible
descriptor structure
• External ZBT SRAM allows large
burst transfers providing efficient
PCI bus utilization.
ZBT RAM Interface
Clock/Reset Control
3 TDMe I/F
Receive
Channel
Mapping
RAM
Interface
Scan +
JTAG
28 T1 Framers I/F
32 E1 Framers I/F
H.100 Bus I/F
3 T3/HSSI I/F
unchannelized
16 xDSL I/F
unchannelized
Serial
Bus
Interface
Receive
Packet/Cell
Engine
Transmit
Packet/Cell
Engine
Transmit
Channel
Mapping
Receive
DMA
32/64-bit
Engine
Arbiter
33/66MHz
PCI 2.1
PCI
Transmit
System
Bus
DMA
Interface
Engine
Utopia
Interface
Utopia
Level 2
General Description
Designed to meet the challenges of
high bandwidth telecommunication line
aggregation devices, and offering an
industry-leading 2048 channels, the
VSC9680 is the HDLC controller and
ATM cell delineation device in Vitesse’
TimeStream™ product family.
Unique Scalable Time-sliced
Architecture
The VSC9680 uses a unique, patent
pending, scalable time-sliced state
machine architecture for performing
packet and cell delineation functions
that increase density and throughput for
a combined full duplex aggregate
throughput of up to 135 Mbps.
The VSC9680 provides more channels
with higher throughput than any cur-
rently available controller device. It in-
cludes a scatter/gather DMA engine,
32/64-bit 33/66 MHz PCI V2.1 compli-
ant bus for system configuration and
HDLC packet transfers, and a Utopia
Level 2 compliant bus for ATM cell
transfers.
Lower Costs, Smaller Board
Space
The VSC9680 can perform HDLC
packet and ATM cell delineation for up
to 2048 logical channels with the low-
est power consumption per channel.
This device can interface directly with
up to 28 T1 or 32 E1 framers, 3
unchannelized DS3 or HSSI channels,
16 xDSL channels, up to 2048 DS0
channels via a H.100 bus, and up to 84
T1 or 63 E1 framers via a proprietary
interface, which eliminates glue logic
requirements, resulting in lower cost
and smaller board space.
www.vitesse.com
Telecom Division
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