74LVT573 View Datasheet(PDF) - Philips Electronics

Part Name

Description

Manufacturer

74LVT573

3.3V Octal D-type transparent latch (3-State)

Philips Electronics 

Philips Semiconductors

3.3V Octal D-type transparent latch

(3-State)

Product specification

74LVT573

FEATURES

• Inputs and outputs on opposite side of package allow easy

interface to microprocessors

• 3-State output buffers

• Common output enable

• TTL input and output switching levels

• Input and output interface capability to systems at 5V supply

• Bus-hold data inputs eliminate the need for external pull-up

resistors to hold unused inputs

• Live insertion/extraction permitted

• No bus current loading when output is tied to 5V bus

• Latch-up protection exceeds 500mA per JEDEC Std 17

• Power-up 3-State

• Power-up reset

• ESD protection exceeds 2000V per MIL STD 883 Method 3015

and 200V per Machine Model

DESCRIPTION

The LVT573 is a high-performance BiCMOS product designed for

VCC operation at 3.3V. This device is an octal transparent latch

coupled to eight 3-State output buffers. The two sections of the

device are controlled independently by Enable (E) and Output

Enable (OE) control gates. The 74LVT573 has a broadside pinout

configuration to facilitate PC board layout and allow easy interface

with microprocessors.

The data on the D inputs are transferred to the latch outputs when

the Latch Enable (E) input is High. The latch remains transparent to

the data inputs while E is High, and stores the data that is present

one setup time before the High-to-Low enable transition.

The 3-State output buffers are designed to drive heavily loaded

3-State buses, MOS memories, or MOS microprocessors. The

active-Low Output Enable (OE) controls all eight 3-State buffers

independent of the latch operation.

When OE is Low, the latched or transparent data appears at the

outputs. When OE is High, the outputs are in the High-impedance

“OFF” state, which means they will neither drive nor load the bus.

QUICK REFERENCE DATA

SYMBOL

PARAMETER

tPLH

tPHL

CIN

COUT

ICCZ

Propagation delay

Dn to Qn

Input capacitance

Output capacitance

Total supply current

CONDITIONS

Tamb = 25°C; GND = 0V

CL = 50pF; VCC = 3.3V

VI = 0V or 3.0V

Outputs disabled; VO = 0V or 3.0V

Outputs disabled; VCC = 3.6V

TYPICAL

2.5

2.7

4

8

.13

UNIT

ns

pF

pF

mA

ORDERING INFORMATION

PACKAGES

20-Pin Plastic SOL

20-Pin Plastic SSOP Type II

20-Pin Plastic TSSOP Type I

TEMPERATURE RANGE

–40°C to +85°C

–40°C to +85°C

–40°C to +85°C

OUTSIDE NORTH AMERICA

74LVT573 D

74LVT573 DB

74LVT573 PW

NORTH AMERICA

74LVT573 D

74LVT573 DB

74LVT573PW DH

DWG NUMBER

SOT163-1

SOT339-1

SOT360-1

PIN CONFIGURATION

OE 1

D0 2

D1 3

D2 4

D3 5

D4 6

D5 7

D6 8

D7 9

GND 10

20 VCC

19 Q0

18 Q1

17 Q2

16 Q3

15 Q4

14 Q5

13 Q6

12 Q7

11 E

SV00031

PIN DESCRIPTION

PIN NUMBER

SYMBOL

1

OE

2, 3, 4, 5, 6, 7, 8, 9

19, 18, 17, 16, 15,

14, 13, 12

D0-D7

Q0-Q7

11

E

10

GND

20

VCC

FUNCTION

Output enable input

(active-Low)

Data inputs

Data outputs

Enable input

(active-High)

Ground (0V)

Positive supply voltage

1998 Feb 19

2

853–1750 18988

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