DatasheetQ Logo
Electronic component search and free download site. Transistors,MosFET ,Diode,Integrated circuits

PA7128PI-15 View Datasheet(PDF) - International Cmos Technology

Part Name
Description
Manufacturer
PA7128PI-15
International-Cmos
International Cmos Technology International-Cmos
PA7128PI-15 Datasheet PDF : 6 Pages
1 2 3 4 5 6
PA7128
A.C. Electrical Characteristics Sequential
Symbol
tSCI
tSCX
tCOI
tCOX
tHX
tSK
tAK
tHK
tSI
tHI
tPK
tSPI
tHPI
tSD
tHD
tSDP
tHDP
tCK
tCW
fMAX1
fMAX2
fMAX3
fMAX4
fTGL
tPR
tST
tAW
tRT
tRTV
tRTC
tRW
tRESET
Parameter6,12
Internal set-up to system clock8 - LCC14
(tAL + tSK + tLC - tCK)
Input16 (EXT.) set-up to system clock, - LCC (tIA + tSCI)
System-clock to Array Int. - LCC/IOC/INC14 (tCK +tLC)
System-clock to Output Ext. - LCC (tCOI + tLO)
Input hold time from system clock - LCC
LCC Input set-up to async. clock13 - LCC
Clock at LCC or IOC - LCC output
LCC input hold time from system clock - LCC
Input set-up to system clock - IOC/INC14 (tSK - tCK)
Input hold time from system clock - IOC/INC14 (tSK - tCK)
Array input to IOC PCLK clock
Input set-up to PCLK clock17 - IOC/INC (tSK-tPK-tIA)
Input hold from PCLK clock17 - IOC/INC (tPK+tIA-tSK)
Input set-up to system clock - IOC/INC Sum-D15
(tIA + tAL + tLC + tSK - tCK)
Input hold time from system clock - IOC Sum-D
Input set-up to PCLK clock
(tIA + tAL + tLC + tSK - tPK) - IOC Sum-D
Input hold time from PCLK clock - IOC Sum-D
System-clock delay to LCC/IOCINC
System-clock low or high pulse width
Max. system-clock frequency Int/Int 1/(tSCI + tCOI)
Max. system-clock frequency Ext/Int 1/(tSCX + tCOI)
Max. system-clock frequency Int/Ext 1/(tSCI + tCOX)
Max. system-clock frequency Ext/Ext 1/(tSCX + tCOX)
Max. system-clock toggle frequency 1/(tCW + tCW)
LCC presents/reset to LCC output
Input to Global Cell present/reset (tIA + tAL + tPR)
Asynch. preset/reset pulse width
Input to LCC Reg-Type (RT)
LCC Reg-Type to LCC output register change
Input to Global Cell register-type change (tRT + tRTV)
Asynch. Reg-Type pulse width
Power-on reset time for registers in clear state2
-20
Min
Max
5
7
7
11
0
2
1
4
0
4
6
0
6
7
0
7
0
6
6
83.3
71.4
62.5
55.5
83.3
1
11
8
7
1
8
10
5
-20 / I-20
Min Max
7
10
9
14
0
2
1
4
0
5
7
0
8
10
0
10
0
7
7
62.5
52.6
47.6
41.6
71.4
2
15
8
9
2
11
10
5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
MHz
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
µs
4 of 6

Share Link: 

datasheetq.com  [ Privacy Policy ]Request Datasheet ] [ Contact Us ]