89C4051 View Datasheet(PDF) - Atmel Corporation

Part Name

Description

Manufacturer

89C4051

8-bit Microcontroller with 4K Bytes Flash

Atmel Corporation 

12. Programming The Flash

The AT89C4051 is shipped with the 4K bytes of on-chip PEROM code memory array in the

erased state (i.e., contents = FFH) and ready to be programmed. The code memory array is pro-

grammed one byte at a time. Once the array is programmed, to re-program any non-blank byte,

the entire memory array needs to be erased electrically.

Internal Address Counter: The AT89C4051 contains an internal PEROM address counter

which is always reset to 000H on the rising edge of RST and is advanced by applying a positive

going pulse to pin XTAL1.

Programming Algorithm: To program the AT89C4051, the following sequence is

recommended.

1. Power-up sequence:

Apply power between VCC and GND pins

Set RST and XTAL1 to GND

2. Set pin RST to “H”

Set pin P3.2 to “H”

3. Apply the appropriate combination of “H” or “L” logic

levels to pins P3.3, P3.4, P3.5, P3.7 to select one of the programming operations

shown in the PEROM Programming Modes table.

To Program and Verify the Array:

4. Apply data for Code byte at location 000H to P1.0 to P1.7.

5. Raise RST to 12V to enable programming.

6. Pulse P3.2 once to program a byte in the PEROM array or the lock bits. The byte-write

cycle is self-timed and typically takes 1.2 ms.

7. To verify the programmed data, lower RST from 12V to logic “H” level and set pins P3.3

to P3.7 to the appropriate levels. Output data can be read at the port P1 pins.

8. To program a byte at the next address location, pulse XTAL1 pin once to advance the

internal address counter. Apply new data to the port P1 pins.

9. Repeat steps 6 through 8, changing data and advancing the address counter for the

entire 4K bytes array or until the end of the object file is reached.

10. Power-off sequence:

set XTAL1 to “L”

set RST to “L”

Turn VCC power off

Data Polling: The AT89C4051 features Data Polling to indicate the end of a write cycle. During

a write cycle, an attempted read of the last byte written will result in the complement of the writ-

ten data on P1.7. Once the write cycle has been completed, true data is valid on all outputs, and

the next cycle may begin. Data Polling may begin any time after a write cycle has been initiated.

Ready/Busy: The Progress of byte programming can also be monitored by the RDY/BSY output

signal. Pin P3.1 is pulled low after P3.2 goes High during programming to indicate BUSY. P3.1 is

pulled High again when programming is done to indicate READY.

8 AT89C4051

1001E–MICRO–6/05

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