A3P030 View Datasheet(PDF) - Unspecified

Part Name

Description

Manufacturer

A3P030

ProASIC®3 Flash Family FPGAs with Optional Soft ARM® Support

Unspecified 

ProASIC3 Flash Family FPGAs

VersaTiles

The ProASIC3 core consists of VersaTiles, which have been enhanced beyond the ProASICPLUS® core tiles. The ProASIC3

VersaTile supports the following:

• All 3-input logic functions—LUT-3 equivalent

• Latch with clear or set

• D-flip-flop with clear or set

• Enable D-flip-flop with clear or set

Refer to Figure 3 for VersaTile configurations.

LUT-3 Equivalent

X1

X2 LUT-3 Y

X3

D-Flip-Flop with Clear or Set

Data

Y

CLK

D-FF

CLR

Enable D-Flip-Flop with Clear or Set

Data

Y

CLK

D-FF

Enable

CLR

Figure 3 • VersaTile Configurations

User Nonvolatile FlashROM

Actel ProASIC3 devices have 1 kbit of on-chip, user-

accessible, nonvolatile FlashROM. The FlashROM can be

used in diverse system applications:

• Internet protocol addressing (wireless or fixed)

• System calibration settings

• Device serialization and/or inventory control

• Subscription-based business models (for example,

set-top boxes)

• Secure key storage for secure communications

algorithms

• Asset management/tracking

• Date stamping

• Version management

The FlashROM is written using the standard ProASIC3

IEEE 1532 JTAG programming interface. The core can be

individually programmed (erased and written), and on-

chip AES decryption can be used selectively to securely

load data over public networks (except in the A3P030

device), as in security keys stored in the FlashROM for a

user design.

The FlashROM can be programmed via the JTAG

programming interface, and its contents can be read

back either through the JTAG programming interface or

via direct FPGA core addressing. Note that the FlashROM

can only be programmed from the JTAG interface and

cannot be programmed from the internal logic array.

The FlashROM is programmed as 8 banks of 128 bits;

however, reading is performed on a byte-by-byte basis

using a synchronous interface. A 7-bit address from the

FPGA core defines which of the 8 banks and which of the

16 bytes within that bank are being read. The three most

significant bits (MSBs) of the FlashROM address

determine the bank, and the four least significant bits

(LSBs) of the FlashROM address define the byte.

The Actel ProASIC3 development software solutions,

Libero® Integrated Design Environment (IDE) and

Designer, have extensive support for the FlashROM. One

such feature is auto-generation of sequential

programming files for applications requiring a unique

serial number in each part. Another feature allows the

inclusion of static data for system version control. Data

for the FlashROM can be generated quickly and easily

using Actel Libero IDE and Designer software tools.

Comprehensive programming file support is also

included to allow for easy programming of large

numbers of parts with differing FlashROM contents.

SRAM and FIFO

ProASIC3 devices (except the A3P030 device) have

embedded SRAM blocks along their north and south

sides. Each variable-aspect-ratio SRAM block is 4,608 bits

in size. Available memory configurations are 256×18,

512×9, 1k×4, 2k×2, and 4k×1 bits. The individual blocks

have independent read and write ports that can be

configured with different bit widths on each port. For

example, data can be sent through a 4-bit port and read

as a single bitstream. The embedded SRAM blocks can be

initialized via the device JTAG port (ROM emulation

mode) using the UJTAG macro (except in the A3P030

device).

8

Product Brief

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