A67P7336 View Datasheet(PDF) - AMIC Technology
Part Name
Description
Manufacturer
A67P7336 Datasheet PDF : 18 Pages
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A67P8318/A67P7336
Pin Description
Pin No.
LQFP (X18)
LQFP (X36)
37
36
35, 34, 33, 32,
100, 99, 82, 81,
44, 45, 46, 47,
48, 49, 50
83
37
36
35, 34, 33, 32,
100, 99, 82, 81,
45, 46, 47, 48,
49, 50
44
93 (BW1)
94 (BW2 )
93 (BW1)
94 (BW2 )
95 (BW3 )
96 (BW4 )
89
89
98
98
92
92
97
97
86
86
85
85
87
87
Symbol
A0
A1
A2 - A9
A11 - A17
A10
BW1
BW2
BW3
BW4
CLK
CE
CE2
CE2
OE
ADV/ LD
CEN
Description
Synchronous Address Inputs : These inputs are registered
and must meet the setup and hold times around the rising
edge of CLK. A0 and A1 are the two lest significant bits
(LSB) of the address field and set the internal burst counter if
burst is desired.
Synchronous Byte Write Enables : These active low inputs
allow individual bytes to be written when a WRITE cycle is
active and must meet the setup and hold times around the
rising edge of CLK. BYTE WRITEs need to be asserted on
the same cycle as the address, BWs are associated with
addresses and apply to subsequent data. BW1 controls I/Oa
pins; BW2 controls I/Ob pins; BW3 controls I/Oc pins;
BW4 controls I/Od pins.
Clock: This signal registers the address, data, chip enables,
byte write enables and burst control inputs on its rising edge.
All synchronous inputs must meet setup and hold times
around the clock are rising edge.
Synchronous Chip Enable : This active low input is used to
enable the device. This input is sampled only when a new
external address is loaded (ADV/LD LOW).
Synchronous Chip Enable : This active low input is used to
enable the device and is sampled only when a new external
address is loaded (ADV/LD LOW). This input can be used
for memory depth expansion.
Synchronous Chip Enable : This active high input is used to
enable the device and is sampled only when a new external
address is loaded (ADV/LD LOW). This input can be used
for memory depth expansion.
Output Enable : This active low asynchronous input enables
the data I/O output drivers.
Synchronous Address Advance/Load : When HIGH, this
input is used to advance the internal burst counter,
controlling burst access after the external address is loaded.
When HIGH, R/ W is ignored. A LOW on this pin permits a
new address to be loaded at CLK rising edge.
Synchronous Clock Enable : This active low input permits
CLK to propagate throughout the device. When HIGH, the
device ignores the CLK input and effectively internally
extends the previous CLK cycle. This input must meet setup
and hold times around the rising edge of CLK.
PRELIMINARY (July, 2005, Version 0.0)
6
AMIC Technology, Corp.
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