A8351601 View Datasheet(PDF) - AMIC Technology
Part Name
Description
Manufacturer
A8351601 Datasheet PDF : 44 Pages
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A8351601 Series
Pin Description
Symbol
ALE
P-DIP
30
EA
31
P0.0-P0.7
32-39
P1.0-P1.7
1-8
P2.0-P2.7
1
2
21-28
Pin No.
PLCC
33
35
36-43
2-9
2
3
24-31
QFP
27
29
30-37
40-44
40
41
18-25
I/O
Description
O Address Latch Enable: Output pulse for latching the low
byte of the address during an address to the external
memory. In normal operation, ALE is emitted at a constant
rate of 1/6 the oscillator frequency, and can be used for
external timing or clocking. Note that one ALE pulse is
skipped during each access to external data memory.
I External Access enable: EA must be externally held low
to enable the device to fetch code from external program
memory locations 0000H to FFFFH. If EA is held high, the
device executes from internal program memory.
I/O Port 0: Port 0 is an 8-bit bidirectional I/O port with internal
pullups. Port 0 pins that have 1s written to them are pulled
high by the internal pullups and can be used as inputs. Port
0 is also the multiplexed low-order address and data bus
during accesses to external program and data memory.
I/O Port 1: Port 1 is an 8-bit bidirectional I/O port with internal
pullups. Port 1 pins that have 1s written to them are pulled
high by the internal pullups and can be used as inputs. As
inputs, Port 1 pins that are externally pulled low will source
current because of the internal pullups. (See DC
Characteristics: IIL).
The Port 1 output buffers can sink/source four TTL inputs.
I T2 (P1.0): Timer/Counter 2 external count input.
I T2EX (P1.1): Timer/Counter 2 trigger input.
I/O Port 2: Port 2 is an 8-bit bidirectional I/O port with internal
pullups. Port 2 pins that have 1s written to them are pulled
high by the internal pullups and can be used as inputs. As
inputs, Port 2 pins that are externally pulled low will source
current because of the internal pullups. (See DC
Characteristics: IIL).
Port 2 emits the high order address byte during fetches
from external program memory and during accesses to
external data memory that used 16-bit addresses (MOVX @
DPTR). In this application, Port 2 uses strong internal
pullups when emitting 1s. During accesses to external data
memory that use 8-bit addresses (MOVX @ Ri [i = 0, 1]),
Port 2 emits the contents of the P2 Special Function
Register.
Port 2 also receives the high-order bits and some control
signals during ROM verification.
(July, 2002, Version 1.0)
4
AMIC Technology, Inc.
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