H1115I View Datasheet(PDF) - Intersil

Part Name

Description

Manufacturer

H1115I

225MHz, Low Power, Output Limiting, Closed Loop Buffer Amplifier

Intersil 

HFA1115

Driving Capacitive Loads

Capacitive loads, such as an A/D input, or an improperly

terminated transmission line degrade the amplifier’s phase

margin resulting in frequency response peaking and

possible oscillations. In most cases, the oscillation can be

avoided by placing a resistor (RS) in series with the output

prior to the capacitance.

Figure 1 details starting points for the selection of this

resistor. The points on the curve indicate the RS and CL

combinations for the optimum bandwidth, stability, and

settling time, but experimental fine tuning is recommended.

Picking a point above or to the right of the curve yields an

overdamped response, while points below or left of the curve

indicate areas of underdamped performance.

RS and CL form a low pass network at the output, thus

limiting system bandwidth well below the amplifier bandwidth

of 200MHz (AV = +1). By decreasing RS as CLincreases (as

illustrated by the curves), the maximum bandwidth is

obtained without sacrificing stability. In spite of this,

bandwidth still decreases as the load capacitance increases.

For example, at AV = +1, RS = 50Ω, CL = 22pF, the overall

bandwidth is 185MHz, but the bandwidth drops to 50MHz at

AV = +1, RS = 15Ω, CL = 330pF.

50

45

40

35

30

25

20

15

10

5

0

0

AV = +2

AV = +1

40 80 120 160 200 240 280 320 360 400

LOAD CAPACITANCE (pF)

FIGURE 1. RECOMMENDED SERIES RESISTOR vs LOAD

CAPACITANCE

Evaluation Board

The performance of the HFA1115 may be evaluated using

the HFA11XX Evaluation Board, slightly modified as follows:

1. 1. Remove the 510Ω feedback resistor (R2), and leave

the connection open.

2. 2. a. For AV = +1 evaluation, remove the 510Ω gain set-

ting resistor (R1), and leave pin 2 floating.

b. For AV = +2, replace the 510Ω gain setting resistor with

a 0Ω resistor to GND.

The layout and modified schematic of the board are shown

in Figure 2.

To order evaluation boards (Part Number HFA11XXEVAL),

please contact your local sales office.

BOARD SCHEMATIC (MODIFIED)

R1 = ∞ (AV = +1) or 0Ω (AV = +2)

R1

1

8

VH

0.1μF

50Ω

2

IN

3

7

50Ω

6

10μF

+5V

OUT

4

10μF 0.1μF

-5V

5

GND

VL

GND

TOP LAYOUT

VH

1

+IN

OUT

VL V-

V+

GND

BOTTOM LAYOUT

FIGURE 2. EVALUATION BOARD SCHEMATIC (AFTER

MODIFICATION FOR BUFFER USE) AND LAYOUT

Limiting Operation

General

The HFA1115 features user programmable output clamps to

limit output voltage excursions. Limiting action is obtained by

applying voltages to the VH and VL terminals (pins 8 and 5)

of the amplifier. VH sets the upper output limit, while VL sets

the lower limit level. If the amplifier tries to drive the output

above VH, or below VL, the clamp circuitry limits the output

voltage at VH or VL (± the limit accuracy), respectively. The

low input bias currents of the limit pins allow them to be

driven by simple resistive divider circuits, or active elements

such as amplifiers or DACs.

Limit Circuitry

Figure 3 shows a simplified schematic of the HFA1115 input

stage, and the high limit (VH) circuitry. As with all current

feedback amplifiers, there is a unity gain buffer (QX1 - QX2)

between the positive and negative inputs. This buffer forces

-IN to track +IN, and sets up a slewing current of:

ISLEW = (V-IN - VOUT)/RF + V-IN/RG

6

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