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ACT8798(2008) View Datasheet(PDF) - Active-Semi, Inc

Part Name
Description
Manufacturer
ACT8798 Datasheet PDF : 34 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
ACT8798
Rev0, 10-Oct-08
PIN DESCRIPTIONS
PIN NAME
DESCRIPTION
1
OUT4
Output Voltage for REG4. Capable of delivering up to 250mA of output current. The output is dis-
charged to G with 650load when disabled.
2
SCL Clock Input for I2C Serial Interface. Data is read on the rising edge of the clock.
3
SDA Data Input for I2C Serial Interface. Data is read on the rising edge of the clock.
4, 17
GA
Analog Ground. Connect GA directly to a quiet ground node. Connect GA, GP12, and GP3 together
at a single point as close to the IC as possible.
5
nMSTR
Master Enable Input. Drive nMSTR to GA or to a logic low to enable the IC. REG1, REG2, and
REG3 are enabled while nMSTR is asserted.
6
nRSTO
Open-Drain Reset Output. nRSTO asserts low for the reset timeout period of 300ms whenever the
IC is enabled.
7
OUT1
Output Feedback Sense for REG1. Connect this pin directly to the output node to connect the inter-
nal feedback network to the output voltage.
8
VP1
Power Input for REG1. Bypass to GP12 with a high quality ceramic capacitor placed as close as
possible to the IC.
9
SW1 Switching Node Output for REG1. Connect this pin to the switching end of the inductor.
10
GP12
Power Ground for REG1 and REG2. Connect GA, GP12, and GP3 together at a single point as
close to the IC as possible.
11
SW2 Switching Node Output for REG2. Connect this pin to the switching end of the inductor.
12
VP2
Power Input for REG2. Bypass to GP12 with a high quality ceramic capacitor placed as close as
possible to the IC.
13
OUT2
Output Feedback Sense for REG2. Connect this pin directly to the output node to connect the inter-
nal feedback network to the output voltage.
14
ON3
Enable Input for REG3, ON3 is functional only when PWRHLD is driven high. Drive ON3 to a logic
high to turn on the REG3. Drive ON3 to a logic low to turn off the REG3.
15
PWRHLD
Power Hold Input. Drive PWRHLD to logic high to enable the IC. Drive PWRHLD to a logic low to
disable all regulators.
16
REFBP
Reference Noise Bypass. Connect a 0.01µF ceramic capacitor from REFBP to GA. This pin is dis-
charged to GA in shutdown.
18
OUT3
Output Feedback Sense for REG3. Connect this pin directly to the output node to connect the inter-
nal feedback network to the output voltage.
19
VP3
Power Input for REG3. Bypass to GP3 with a high quality ceramic capacitor placed as close as
possible to the IC.
20
SW3 Switching Node Output for REG3. Connect this pin to the switching end of the inductor.
21
GP3
Power Ground for REG3. Connect GA, GP12, and GP3 together at a single point as close to the IC
as possible.
22
OUT5
Output Voltage for REG5. Capable of delivering up to 250mA of output current. The output is dis-
charged to G with 650load when disabled.
23
OUT6
Output Voltage for REG6. Capable of delivering up to 250mA of output current. The output is dis-
charged to G with 650load when disabled.
24
INL
Power Input for REG4, REG5 and REG6. Bypass to GA with a high quality ceramic capacitor
placed as close as possible to the IC.
EP
EP Exposed Pad. Must be soldered to ground on PCB.
Innovative PowerTM
-4-
ActivePMUTM is a trademark of Active-Semi.
I2CTM is a trademark of Philips Electronics.
www.active-semi.com
Copyright © 2008 Active-Semi, Inc.

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