AD102JY View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
AD102JY Datasheet PDF : 6 Pages
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AD102/AD104
Although this circuit generates a unipolar clock output of
0 V–15 V, any 15 V amplitude square wave at 25 kHz with a
duty cycle of 50% is acceptable. This is possible since the
AD104 clock input is ac coupled by means of a 0.1 µF capacitor
as shown in Figure 6. The source, therefore, only needs to be
± 7.5 V p-p in total amplitude and may be offset as desired. A
recommended maximum amplitude limit of ± 15 V with respect
to PWR/CLK COM should not be exceeded.
0.1µF
T
R
8
CLK IN
A
N
+V
S
–V
F
O
R
0.1µF 0.1µF
M
2
PWR/CLK
E
R
COM
AD104
Figure 6. AD104 Clock Input
One clock circuit will usually drive multiple AD104s (typically
4, 8 or 16 units). If many AD104s are to be operated from a
single source, external bypass capacitors should be used with a
value of at least 1 µF for every five isolators used. Place the
capacitor as close as possible to the clock driver.
Input Configuration
The AD102 and AD104 are very easy to use in a wide range of
applications. The input stage connections (IN+, IN–, FB,
ICOM) approximate a “vanilla” type op amp input and may for
all intents and purposes be treated as such. Most any typical cir-
cuit connection that is valid for a standard op amp can be
accommodated, so long as it is expected to perform within
the specifications herein (i.e., limited gain and bandwidth
parameters).
Figure 7 shows the most common input configuration, which is
unity gain operation. This configuration is appropriate where
the input signal is within the range of ± 5 V or where larger sig-
nals have been previously attenuated, usually by means of a tra-
ditional resistor divider technique.
VSIG
(±5V)
3
6
5
2kΩ
(SEE TEXT)
4
FB
IN–
IN+
ICOM
ISOLATION
BARRIER
AMPLIFIER
AND
MODULATOR
OUT HI
1
OUT LO 9
AD102
OR
AD104
±15VDC 7
CLOCK IN 8
COMMON 2
VOUT
(±5V)
±15VDC (AD102)
OR
CLOCK (AD104)
For gains larger than unity, the addition of a gain and feedback
resistor allows amplification of smaller signals up to a higher
level. Whenever practical, any low level signal should be ampli-
fied to meet a full ± 5 V output swing. This helps reduce the
effective output ripple contribution introduced to the original
signal during modulation, isolation and subsequent filtering as
seen at the output.
100pF
2kΩ
VSIG
(±5V)
FB
3
RF
6
5
RG
4
IN –
IN +
ICOM
ISOLATION
BARRIER
AMPLIFIER
OUT HI
1
AND
MODULATOR
OUT LO
9
AD102
OR
AD104
VOUT = VSIG
RF ≥ 20kΩ
x
(
1
+
RF
RG
)
VOUT
(±5V)
Figure 8. Input Connection for Gain > 1
When taking a gain of more than 5 V/V, addition of a 100 pF
capacitor is recommended; it is not needed at lower gains, but if
used will not adversely affect operation. Additionally, whenever
the isolation amplifier is not powered, a negative input voltage
of approximately 2 V may cause an input current to flow. If the
signal source can supply more than a few mA of current, a 2 kΩ
limiting resistor in series with IN+ is recommended. This is es-
pecially advised when using AD102s as they may not power up
properly with a high input current present, (see Figures 7 and 8
for examples).
Synchronization
Since the AD104 operates from a common clock, synchroniza-
tion is inherent. AD102s will normally not interact to produce
beat frequencies even when mounted on 0.3 inch centers. Inter-
action may occur in very rare situations where a large number of
long, unshielded input cables are bundled together. In such
cases, shielded cable may be required or AD104s can be used.
For related information and application examples refer to the
AD202/AD204 and AD210 data sheets.
Figure 7. Unity Gain Application
REV. A
–5–
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