AD1836A View Datasheet(PDF) - Analog Devices
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AD1836A Datasheet PDF : 24 Pages
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AD1836A
Table 19. ADC Control Register 3
When changing clock mode, other SPI bits that are written during the same SPI transaction may be lost. Therefore, it is recommended
that these be set separately.
Address
15, 14,
13, 12
1110
RD/WR
11
0
Reserved
10, 9, 8
000
Clock Mode
7, 6
00 = 256 × fS
01 = 512 × fS
10 = 768 × fS
Function
Left Differential
I/P Select
5
0 = Differential
PGA Mode
1 = PGA/MUX
Mode (Single-
Ended Input)
Right
Differential
I/P Select
4
Left
MUX/PGA
Enable
3
0 = Differential
PGA Mode
1 = PGA/MUX
Mode (Single-
Ended Input)
0 = Direct
1 = MUX/PGA
Left MUX
I/P Select
2
Right
MUX/PGA
Enable
1
0 = I/P 0 0 = Direct
1 = I/P 1 1 = MUX/PGA
Right
MUX I/P
Select
0
0 = I/P 0
1 = I/P 1
Table 20. ADC Peak Level Data Registers
Address
15, 14, 13, 12
1000 = ADC1L
1001 = ADC1R
1010 = ADC2L
1011 = ADC2R
RD/WR
11
1
Reserved
10
0
Peak Level Data (10 Bits)
6 Data Bits
9:4
000000 = 0.0 dBFS
000001 = –1.0 dBFS
000010 = –2.0 dBFS
000011 = –3.0 dBFS
4 Fixed Bits
3:0
0000
The 4 LSBs are always zero.
111100 = –60 dBFS Min
Rev. 0 | Page 21 of 24
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