AD1896AYRS View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
AD1896AYRS Datasheet PDF : 28 Pages
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DIGITAL TIMING (–40؇C < TA < +105؇C, VDD_CORE = 3.3 V ؎ 5%, VDD_IO = 5.0 V ؎ 10%)
Parameter1
Min
Typ
tMCLKI
MCLK_I Period
33.3
fMCLK
MCLK_I Frequency
tMPWH
MCLK_I Pulsewidth High
9
tMPWL
MCLK_I Pulsewidth Low
12
Input Serial Port Timing
tLRIS
LRCLK_I Setup to SCLK_I
8
tSIH
SCLK_I Pulsewidth High
8
tSIL
SCLK_I Pulsewidth Low
8
tDIS
SDATA_I Setup to SCLK_I Rising Edge
8
tDIH
SDATA_I Hold from SCLK_I Rising Edge
3
Propagation Delay from MCLK_I Rising Edge to SCLK_I Rising Edge
(Serial Input Port MASTER)
Propagation Delay from MCLK_I Rising Edge to LRCLK_I Rising Edge
(Serial Input Port MASTER)
Output Serial Port Timing
tTDMS
TDM_IN Setup to SCLK_O Falling Edge
3
tTDMH
TDM_IN Hold from SCLK_O Falling Edge
3
tDOPD
SDATA_O Propagation Delay from SCLK_O, LRCLK_O
tDOH
SDATA_O Hold from SCLK_O
3
tLROS
LRCLK_O Setup to SCLK_O (TDM Mode Only)
5
tLROH
LRCLK_O Hold from SCLK_O (TDM Mode Only)
3
tSOH
SCLK_O Pulsewidth High
10
tSOL
SCLK_O Pulsewidth Low
5
tRSTL
RESET Pulsewidth Low
200
Propagation Delay from MCLK_I Rising Edge to SCLK_O Rising Edge
(Serial Output Port MASTER)
Propagation Delay from MCLK_I Rising Edge to LRCLK_O Rising Edge
(Serial Output Port MASTER)
NOTES
1Refer to Timing Diagrams section.
2The maximum possible sample rate is: FSMAX = fMCLK /138.
3fMCLK of up to 34 MHz is possible under the following conditions: 0∞C < TA < 70∞C, 45/55 or better MCLK_I duty cycle.
Specifications subject to change without notice.
AD1896
Max
30.02, 3
12
12
20
12
12
Unit
ns
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
REV. A
–3–
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