EVAL-AD1938AZ(RevB) View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
EVAL-AD1938AZ Datasheet PDF : 32 Pages
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AD1928
DIGITAL FILTERS
Table 6.
Parameter
Mode
Factor
Min Typ
Max
Unit
ADC DECIMATION FILTER
All modes, typ @ 48 kHz
Pass Band
0.4375 fS
21
kHz
Pass-Band Ripple
±0.015
dB
Transition Band
0.5 fS
24
kHz
Stop Band
0.5625 fS
27
kHz
Stop-Band Attenuation
79
dB
Group Delay
22.9844/fS
479
μs
DAC INTERPOLATION FILTER
Pass Band
Pass-Band Ripple
E Transition Band
T Stop Band
E Stop-Band Attenuation
L Group Delay
48 kHz mode, typ @ 48 kHz
96 kHz mode, typ @ 96 kHz
192 kHz mode, typ @ 192 kHz
48 kHz mode, typ @ 48 kHz
96 kHz mode, typ @ 96 kHz
192 kHz mode, typ @ 192 kHz
48 kHz mode, typ @ 48 kHz
96 kHz mode, typ @ 96 kHz
192 kHz mode, typ @ 192 kHz
48 kHz mode, typ @ 48 kHz
96 kHz mode, typ @ 96 kHz
192 kHz mode, typ @ 192 kHz
48 kHz mode, typ @ 48 kHz
96 kHz mode, typ @ 96 kHz
192 kHz mode, typ @ 192 kHz
48 kHz mode, typ @ 48 kHz
96 kHz mode, typ @ 96 kHz
192 kHz mode, typ @ 192 kHz
0.4535 fS
0.3646 fS
0.3646 fS
0.5 fS
0.5 fS
0.5 fS
0.5465 fS
0.6354 fS
0.6354 fS
25/fS
11/fS
8/fS
22
35
70
24
48
96
26
61
122
70
70
70
521
115
42
±0.01
±0.05
±0.1
O TIMING SPECIFICATIONS
−40°C < TC < 125°C, DVDD = 3.3 V ± 10%.
S Table 7.
Parameter
INPUT MASTER CLOCK (MCLK) AND
B RESET
O tMH
Condition
Comments
Min Max
MCLK duty cycle DAC/ADC clock source = PLL clock @ 256 fS,
384 fS, 512 fS, and 768 fS
40
60
DAC/ADC clock source = direct MCLK @ 512 fS 40
60
(bypass on-chip PLL)
kHz
kHz
kHz
dB
dB
dB
kHz
kHz
kHz
kHz
kHz
kHz
dB
dB
dB
μs
μs
μs
Unit
%
%
fMCLK
MCLK frequency PLL mode, 256 fS reference
6.9 13.8 MHz
Direct 512 fS mode
27.6 MHz
tPDR
RST low
15
ns
tPDRR
RST recovery
Reset to active output
4096
tMCLK
PLL
Lock Time
MCLK and LR
clock input
10 ms
256 fS VCO Clock Output Duty Cycle MCLKO/XO pin
40
60
%
Rev. B | Page 6 of 32
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