EVAL-AD1938AZ(RevB) View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
EVAL-AD1938AZ Datasheet PDF : 32 Pages
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AD1928
Parameter
Condition
Comments
Min Max Unit
SPI PORT
See Figure 11, except where otherwise noted
tCCH
CCLK high
35
ns
tCCL
CCLK low
35
ns
fCCLK
CCLK frequency fCCLK = 1/tCCP, only tCCP shown in Figure 11
10 MHz
tCDS
CIN setup
To CCLK rising
10
ns
tCDH
CIN hold
From CCLK rising
10
ns
tCLS
CLATCH setup
To CCLK rising
10
ns
tCLH
CLATCH hold
From CCLK falling
10
ns
tCLHIGH
CLATCH high
Not shown in Figure 11
10
ns
tCOE
COUT enable
From CCLK falling
30 ns
tCOD
tCOH
tCOTS
DAC SERIAL PORT
tDBH
tDBL
tDLS
tDLH
tDLSKEW
tDDS
tDDH
ADC SERIAL PORT
tABH
tABL
tALS
tALH
tALSKEW
tABDD
AUXILIARY INTERFACE
tAXDS
tAXDH
tDXDD
tXBH
tXBL
tDLS
tDLH
COUT delay
From CCLK falling
COUT hold
From CCLK falling, not shown in Figure 11
30
COUT tristate
From CCLK falling
See Figure 24
DBCLK high
Slave mode
10
E DBCLK low
Slave mode
10
DLRCLK setup
To DBCLK rising, slave mode
10
DLRCLK hold
From DBCLK rising, slave mode
5
T DLRCLK skew
From DBCLK falling, master mode
−8
DSDATA setup
To DBCLK rising
10
DSDATA hold
From DBCLK rising
5
See Figure 25
E ABCLK high
Slave mode
10
ABCLK low
Slave mode
10
ALRCLK setup
To ABCLK rising, slave mode
10
L ALRCLK hold
From ABCLK rising, slave mode
5
ALRCLK skew
From ABCLK falling, master mode
−8
ASDATA delay
From ABCLK falling
O AAUXDATA setup To AUXBCLK rising
10
AAUXDATA hold From AUXBCLK rising
5
DAUXDATA delay From AUXBCLK falling
SAUXBCLK high
10
AUXBCLK low
10
AUXLRCLK setup To AUXBCLK rising
10
OBAUXLRCLK hold From AUXBCLK rising
5
30
30
+8
+8
18
18
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Rev. B | Page 7 of 32
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