AD28MSP02 View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
AD28MSP02 Datasheet PDF : 20 Pages
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AD28msp02
The IIR low-pass filter is a 10th-order elliptic filter with a pass-
band edge at 3.70 kHz and a stopband attenuation of 65 dB at
4 kHz. This filter has the following specifications:
Filter type:
Sample frequency:
Passband cutoff:*
Passband ripple:
Stopband cutoff:
Stopband ripple:
l0th-order low-pass elliptic IIR
40.0 kHz
3.70 kHz
± 0.2 dB
4.0 kHz
–65.00 dB
*The passband cutoff frequency is defined to be the last point in the passband
that meets the passband ripple specification.
(Note that these specifications apply only to this filter, and not to the entire
DAC. The specifications can be used to perform further analysis of the exact
characteristics of the filter, for example using a digital filter design software
package.)
Figure 2 shows the frequency response of the IIR low-pass filter.
Passband ripple is ± 0.2 dB for the combined effects of the
DAC’s digital filters (i.e., high-pass filter and IIR low pass of the
interpolation filter) in the 300 Hz–3400 Hz passband.
Analog Smoothing Filter and Programmable Gain Amplifier
The programmable gain amplifier (PGA) can be used to adjust
the output signal level by –15 dB to +6 dB. This gain is selected
by bits 7–9 (OG0, OG1, OG2) of the AD28msp02’s control
register.
The AD28msp02’s analog smoothing filter consists of a 2nd-
order Sallen-Key continuous-time filter and a 3rd-order
switched capacitor filter. The Sallen-Key filter has a 3 dB point
at approximately 80 kHz.
Differential Output Amplifier
The AD28msp02’s analog output (VOUTP, VOUTN) is pro-
duced by a differential output amplifier. The differential ampli-
fier can drive loads of 2 kΩ or greater and has a maximum
differential output voltage swing of ± 3.156 V peak-to-peak
(3.17 dBm0). The output signal is dc-biased to the
AD28msp02’s on-chip voltage reference (VREF) and can be
ac-coupled directly to a load or dc-coupled to an external ampli-
fier. Refer to “Analog Output” in the “Design Considerations”
section of this data sheet for more information.
The VOUTP–VOUTN outputs must be used as differential out-
puts; do not use either as a single-ended output.
SERIAL PORT
The AD28msp02 communicates with a host processor via the
bidirectional synchronous serial port (SPORT). The SPORT is
used to transmit and receive digital data and control information.
All serial transfers are 16 bits long, MSB first. Data bits are
transferred at the serial clock rate (SCLK). SCLK equals the
master clock frequency divided by 5. SCLK = 2.6 MHz for the
master clock frequency MCLK = 13.0 MHz.
Host Processor Interface
The AD28msp02-to-host processor interface is shown in Figure 4.
AD28msp02
SDO
SDOFS
SCLK
DATA/CNTRL
SDI
SDIFS
Host Processor
SERIAL DATA RECEIVE
RECEIVE FRAME SYNC
SERIAL CLOCK
FLAG
SERIAL DATA TRANSMIT
TRANSMIT FRAME SYNC
Figure 4. AD28msp02-to-Host Processor Interface
Table I describes the SPORT signals and how they are used to
communicate with the host processor. The AD28msp02’s chip
select (CS) must be held high to enable SPORT operation. CS
can be used to 3-state the SPORT pins and disable communica-
tion with the host processor.
To use the ADSP-2101 or ADSP-2111 as host DSP processor
for the AD28msp02, the following connections can be used (as
shown in Figure 5):
AD28msp02 Pin
SCLK
–
SDO
–
SDOFS
–
SDI
–
SDIFS
–
DATA/CNTRL
–
ADSP-2101/2111 Pin
SCLK0
DR0
RFS0
DT0
TFS0
FO (Flag Output)
Signal
Name
SCLK
SDO
SDOFS
SDI
SDIFS
Description
Serial clock
Serial data output
Serial data output frame sync
Serial data input
Serial data input frame sync
Table I. SPORT Signals
Generated By
Signal State When
RESET Low (CS High)
AD28msp02
Low
AD28msp02
Low
AD28msp02
Low
Host Processor
—
Host Processor
—
Signal State During
Powerdown (CS High)
Active
Active*
Low
—
—
(CS must be held high to enable SPORT operation.)
*Outputs last data value that was valid prior to entering powerdown.
–4–
REV. 0
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