AD5100(Rev0) View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
AD5100
(Rev.:Rev0)
(Rev.:Rev0)
Analog Devices
AD5100 Datasheet PDF : 36 Pages
| |||
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
AD5100
V1MON 1
GND 2
16 V2MON
15 GND/NC
VOTP 3
14 V4MON
V3MON 4 AD5100 13 AD0
TOP VIEW
MR 5 (Not to Scale) 12 SHDN
WDI 6
11 SHDNWARN
SCL 7
SDA 8
10 V4OUT
9 RESET
NC = NO CONNECT
Figure 3. Pin Configuration
Table 5. AD5100 Pin Function Descriptions
Pin No. Mnemonic Description
1
V1MON
2
GND
High Voltage Monitoring Input. AD5100 internal supply is derived from V1MON. There must be a 10 μF electrolytic
capacitor between this pin and GND, placed as close as possible to the V1MON pin.
Ground.
3
VOTP
One-Time Programmable Supply Voltage for EPROM. A 10 μF decoupling capacitor (low ESR) to GND is required
when not fuse programming.
4
V3MON
Low Voltage Monitoring Input.
5
MR
Manual Reset Input. Active low.
6
WDI
Watchdog Input.
7
SCL
I2C Serial Input Register Clock. Open-drain input. If it is driven directly from a logic driver without the pull-up
resistor, ensure that the VIH minimum is 3.3 V.
8
SDA
I2C Serial Data Input/Output. Open-drain input/output. If it is driven directly from a logic driver without the pull-
up resistor, ensure that the VIH minimum is 3.3 V.
9
RESET
Reset. Push-pull output with rail voltage of V3MON.
10
V4OUT
Open-Drain Output. Triggered by V4MON.
11
SHDNWARN Shutdown Warning. Active low, open-drain output.
12
SHDN
Shutdown Output. Push-pull output with selectable rail voltage of V1MON or VREG, the AD5100 internal power (30 V
maximum).
13
AD0
I2C Slave Address Configuration. If tied high, this pin can only be tied to 3.3 V maximum.
14
V4MON
Low Voltage Monitoring Input. Capable of withstanding 30 V.
15
GND/NC
Ground/No Connect. Can be grounded or left floating but do not connect to any other potentials.
16
V2MON
High Voltage Monitoring Input. It is also the internal supply voltage enabling input.
GND
1
16
2
15
3
14
4 AD5100 13
TOP VIEW
5 (Not to Scale) 12
6
11
7
10
8
9
Figure 4. Recommended PCB Layout for Shielded High Voltage Inputs
Rev. 0 | Page 9 of 36
Share Link: