AD5171(RevPrC) View Datasheet(PDF) - Analog Devices
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AD5171 Datasheet PDF : 20 Pages
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Preliminary Technical Data
THEORY OF OPERATION
The AD5171 allows unlimited 6-bit adjustments, except for one-
time programmable, set-and-forget resistance setting. OTP
technology is a proven cost-effective alternative over EEMEM
in one-time memory programming applications. AD5171
employs fuse link technology to achieve the memory retention
of the resistance setting function. It comprises six data fuses,
which control the address decoder for programming the RDAC,
one user mode test fuse for checking setup error, and one
programming lock fuse for disabling any further programming
once the data fuses are blown.
ONE-TIME PROGRAMMING (OTP)
Prior to OTP activation, the AD5171 presets to midscale during
power on. After the wiper is set at the desired position, the
resistance can be permanently set by programming the T bit to
high along with the proper coding (Table 7).
The device control circuit has two validation bits, E1 and E0,
that can be read back in the read mode for checking the
programming status as shown in Table 4.
Table 4. Validation Status
E1 E0 Status
0
0 Ready for Programming
0
1 Test Fuse Not Blown Successfully. (For factory
setup checking purpose only. Users should not
see these combinations.)
1
0 Error. Some fuses are not blown. Try again.
1
1 Successful. No further programming is possible.
When the OTP T bit is set, the internal clock is enabled. The
program will attempt to blow a test fuse. The operation stops if
this fuse is not blown properly. The validation Bits E1 and E0
show 01, and the users should check the setup. If the test fuse is
blown successfully, the data fuses will be programmed next. The
six data fuses will be programmed in six clock cycles. The
output of the fuses is compared with the code stored in the
DAC register. If they do not match, E1 and E0 = 10 is issued as a
error and the operation stops. Users may retry with the same
codes. If the output and stored code match, the programming
lock fuse will be blown so that no further programming is
possible. In the meantime, E1 and E0 will issue 11 indicating the
lock fuse is blown successfully. All the fuse latches are enabled at
power-on and therefore the output corresponds to the stored
setting from this point on. Figure 24 shows a detailed functional
block diagram.
AD5171
A
SCL
SDA
I2C INTERFACE
DAC
REG.
MUX
DECODER
W
B
COMPARATOR
ONE-TIME
PROGRAM/TEST
CONTROL BLOCK
FUSES
EN
FUSE
REG.
Figure 24. Detailed Functional Block Diagram
DETERMINING THE VARIABLE RESISTANCE
AND VOLTAGE
Rheostat Mode Operation
If only the W-to-B or W-to-A terminals are used as variable
resistors, the unused terminal can be opened or shorted with W.
This operation is called rheostat mode (Figure 25).
A
W
A
W
A
W
B
B
B
Figure 25. Rheostat Mode Configuration
The nominal resistance (RAB) of the RDAC has 64 contact
points accessed by the wiper terminal, plus the B terminal
contact if RWB is considered. The 6-bit data in the RDAC latch is
decoded to select one of the 64 settings. Assuming that a 10 kΩ
part is used, the wiper’s first connection starts at the B terminal
for data 0x00. Such connection yields a minimum of 60 Ω
resistance between terminals W and B because of the 60 Ω
wiper contact resistance. The second connection is the first tap
point, which corresponds to 219 Ω (RWB = (1) × RAB/63 + RW)
for data 0x01, and so on. Each LSB data value increase moves
the wiper up the resistor ladder until the last tap point is
reached at 10060 Ω ((63) × RAB/63 + RW). Figure 26 shows a
simplified diagram of the equivalent RDAC circuit. The general
equation determining RWB is
RWB (D)
=
D
63
×
RAB
+
RW
(1)
where:
D is the decimal equivalent of the 6-bit binary code.
RAB is the end-to-end resistance.
RW is the wiper resistance contributed by the on-resistance of
the internal switch.
Rev. PrC | Page 11 of 20
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