AD5273BRJ10-R2 View Datasheet(PDF) - Analog Devices
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Description
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AD5273BRJ10-R2 Datasheet PDF : 20 Pages
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AD5273
THEORY OF OPERATION
The AD5273 is a One-Time-Programmable (OTP), Set-and-
Forget, 6-bit digital potentiometer. It is comprised of six data
fuses, which control the address decoder for programming the
RDAC, one user mode test fuse for checking setup error, and one
programming lock fuse for disabling any further programming
once the data fuses are programmed correctly.
One-Time-Programming (OTP)
AD5273 has an internal power-on preset that places the wiper
in the midscale during power-on. After the wiper is adjusted to
the desired position, the wiper setting can be permanently pro-
grammed by setting the T bit, MSB of the Instruction Byte, to 1
along with the proper coding. Refer to Table I.
The one-time program control circuit has two validation bits, E1
and E0, that can be read back in the Read mode for checking the
programming status. Table III shows the validation status.
Table III. Validation Status
E1 E0 Status
0 0 Ready for Programming
0 1 Test Fuse Not Blown Successfully (For Setup Checking)
1 0 Fatal Error. Some fuses are not blown. Retry.
1 1 Successful. No further programming is possible.
The detailed programming sequence is explained further below.
When the OTP T bit is set, the internal clock is enabled. The
program will attempt to blow a test fuse. The operation stops if
this fuse is not blown successfully. The validation bits, E1 and E0,
show 01 and the users should check the setup. If the test fuse is
blown successfully, the data fuses will be programmed next. The
six data fuses will be programmed in six clock cycles. The output
of the fuses is compared with the code stored in the DAC regis-
ter. If they do not match, E1 E0 = 10 is issued as a fatal error and
the operation stops. Users may retry with the same code. If the
output and the stored code match, the programming lock fuse
will be blown so that no further programming is possible. In the
meantime, E1 E0 will issue 11 indicating the lock fuse is blown
successfully. All the fuse latches are enabled at power on from this
point on. Figure 2 shows a detailed functional block diagram.
DETERMINING THE VARIABLE RESISTANCE AND
VOLTAGE*
Rheostat Operation
The nominal resistance of the RDAC between terminals A and B
is available in 1 k⍀, 10 k⍀, 50 k⍀, and 100 k⍀.The final two or
three digits of the part number determine the nominal resistance
value, e.g., 1 k⍀ = 1, 10 k⍀ = 10; 50 k⍀ = 50; 100 k⍀ = 100. The
nominal resistance (RAB) of the RDAC has 64 contact points
accessed by the wiper terminal, plus the B terminal contact. The
6-bit data in the RDAC latch is decoded to select one of the 64
possible settings. Assuming that a 10 k⍀ part is used, the wiper’s
first connection starts at the B terminal for data 00H. Since there
is a 60 ⍀ wiper contact resistance, such connection yields a
minimum of 60 ⍀ resistance between terminals W and B. The
second connection is the first tap point and corresponds to 219 ⍀
(RWB = RAB/63 + RW = 159 + 60) for data 01H. The third con-
nection is the next tap point representing 378 ⍀ (159 ϫ 2 + 60)
for data 02H, and so on. Each LSB data value increase moves the
wiper up the resistor ladder until the last tap point is reached at
10060 ⍀ [RAB + RW]. Figure 3 shows a simplified diagram of the
equivalent RDAC circuit. The general equation determining the
digitally programmed output resistance between W and B is:
( ) RWB
D
=
D
63
¥ RAB
+ RW
(1)
where:
D is the decimal equivalent of the binary code loaded in the 6-bit
RDAC register.
RAB is the nominal end-to-end resistance.
RW is the wiper resistance contributed by the on resistance of the
internal switch.
Again, if RAB = 10 k⍀ and terminal A is opened, the following
output resistance values RWB will be set for the following RDAC
latch codes.
D(DEC)
63
32
1
0
R WB (⍀)
10060
5139
219
60
Output State
Full-Scale (RAB + RW)
Midscale
1 LSB
Zero-Scale (Wiper contact resistance)
*Applies to Potentiometer Mode only
A
SCL
SDA
I2C INTERFACE
DAC
REG.
MUX
DECODER
W
B
COMPARATOR
ONE TIME
PROGRAM/TEST
CONTROL BLOCK
FUSES
EN
FUSE
REG.
REV. 0
Figure 2. Detailed Functional Block Diagram
–11–
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