AD5273BRJ10-REEL7 View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
AD5273BRJ10-REEL7 Datasheet PDF : 20 Pages
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AD5273
Parameter
Symbol Conditions
Min Typ Max Unit
DYNAMIC CHARACTERISTICS6, 10, 11
Bandwidth –3 dB
Total Harmonic Distortion
Adjustment Settling Time
OTP Settling Time12
Power-Up Settling Time –
BW_1 k RAB = 1 k, Code = 20H
BW_10 k RAB = 10 k, Code = 20H
BW_50 k RAB = 50 k, Code = 20H
BW_100 k RAB = 100 k, Code = 20H
THDW
VA = 1 V rms, RAB = 1 k,
VB = 0 V, f = 1 kHz
tS1
VA = 5 V ± 1 LSB Error Band, VB = 0,
Measured at VW
tS_OTP
VA = 5 V ± 1 LSB Error Band, VB = 0,
Measured at VW
Post Fuses Blown
Resistor Noise Voltage
tS2
eN_WB
VA = 5 V ± 1 LSB Error Band, VB = 0,
Measured at VW
RAB = 1 k, f = 1 kHz, Code = 20H
RAB = 20 k, f = 1 kHz, Code = 20H
RAB = 50 k, f = 1 kHz, Code = 20H
RAB = 100 k, f = 1 kHz, Code = 20H
INTERFACE TIMING CHARACTERISTICS (applies to all parts6, 11, 13)
SCL Clock Frequency
fSCL
tBUF Bus Free Time between
STOP and START
t1
1.3
tHD;STA Hold Time
(repeated START)
t2
After this period, the first clock
pulse is generated.
0.6
tLOW Low Period of SCL Clock
t3
1.3
tHIGH High Period of SCL Clock
t4
0.6
tSU;STA Setup Time for START
Condition
t5
0.6
tHD;DAT Data Hold Time
t6
tSU;DAT Data Setup Time
t7
0.1
tF Fall Time of Both SDA and
SCL Signals
t8
tR Rise Time of Both SDA and
SCL Signals
t9
tSU;STO Setup Time for STOP
Condition
t10
0.6
6000
600
110
60
0.014
5
400
5
3
13
20
28
400
50
0.9
0.3
0.3
kHz
kHz
kHz
kHz
%
µs
ms
µs
nV/√Hz
nV/√Hz
nV/√Hz
nV/√Hz
kHz
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
NOTES
1Typicals represent average readings at 25°C, VDD = 5 V, VSS = 0 V.
2Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions.
R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.
3VAB = VDD, Wiper (VW) = No Connect.
4INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter.VA = VDD and VB = 0 V. DNL specification
limits of ±1 LSB maximum are guaranteed monotonic operating conditions.
5Resistor terminals A, B, W have no limitations on polarity with respect to each other.
6Guaranteed by design and not subject to production test.
7Different from operating power supply, power supply for OTP is used one time only.
8Different from operating current, supply current for OTP lasts approximately 400 ms for one time needed only.
9PDISS is calculated from (IDD VDD). CMOS logic level inputs result in minimum power dissipation.
10 Bandwidth, noise, and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest bandwidth.
The highest R value results in the minimum overall power consumption.
11 All dynamic characteristics use VDD = 5 V.
12 Different from settling time after fuses are blown. The OTP settling time occurs once only.
13 See Figure 1 for location of measured values.
Specifications subject to change without notice.
REV. 0
–3–
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