AD6645 View Datasheet(PDF) - Analog Devices

Part Name

Description

Manufacturer

AD6645

14-Bit, 80 MSPS/105 MSPS A/D Converter

Analog Devices 

AD6645

Parameter

DATA-READY (DRY4)/DATA(D13:0),, OVR

Data-Ready to DATA Delay (Hold Time)

50% Duty Cycle

Data-Ready to DATA Delay (Setup Time)

50% Duty Cycle

APERTURE DELAY

APERTURE UNCERTAINTY (JITTER)

Symbol

tH_DR

tS_DR

tA

tJ

Temp

Full

Full

Full

Full

25°C

25°C

Test

Level

V

V

V

V

V

V

AD6645ASQ-80/

AD6645ASV-80

Min Typ

Max

Note 55

6.6

7.2

7.9

Note 55

2.1

3.6

5.1

−500

0.1

AD6645ASQ-105/

AD6645ASV-105

Min Typ

Max

Note 55

5.1

5.7

6.4

Note 55

0.6

2.1

3.5

−500

0.1

1 Several timing parameters are a function of tENC and tENCH.

2 Several timing parameters are a function of tENCL and tENCH.

3 ENCODE TO DATA Delay (Hold Time) is the absolute minimum propagation delay through the ADC, tE_RL = tH_E.

4 DRY is an inverted and delayed version of the encode clock. Any change in the duty cycle of the clock will correspondingly change the duty cycle of DRY.

5 Data-ready to DATA Delay (tH_DR and tS_DR) is calculated relative to rated speed grade and is dependent on tENC and duty cycle.

Unit

ns

ns

ps

ps rms

tA

N

AIN

N+1

N+2

N+3

ENCODE,

ENCODE

tE_RL

D[13:0], OVR

DRY

tENC

N

tE_FL

tENCH

N+1

N–3

tENCL

N–2

N+2

tE_DR

tS_DR

N+3

tS_E

N–1

tH_DR

tDR

Figure 2. Timing Diagram

N+4

N+4

tH_E

N

Rev. D | Page 6 of 24

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