AD71028JST View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
AD71028JST Datasheet PDF : 20 Pages
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AD71028
PIN CONFIGURATION AND FUNCTIONAL DESCRIPTIONS
48 47 46 45 44 43 42 41 40 39 38 37
DIV2_PA 1
DIV1_PB 2
DIV2_PB 3
NC 4
NC 5
DGND 6
DVDD 7
ODVDD 8
NC 9
NC 10
COUT 11
CDATA 12
AD71028
TOP VIEW
(Not to Scale)
36 AGND
35 OUTB–
34 OUTB+
33 AVDD
32 AGND
31 AVDD
30 OUTA+
29 OUTA–
28 AGND
27 NC
26 NC
25 DOUBLE
13 14 15 16 17 18 19 20 21 22 23 24
NC = NO CONNECT
Figure 2. 48-Lead Low Profile Quad Flat Pack (LQFP)
Table 9. Pin Function Descriptions
Pin No.
Mnemonic
1
DIV2_PA
2
DIV1_PB
3
DIV2_PB
4, 5, 9, 10, 26, 27, 39 NC
6, 16, 44
DGND
7, 13, 17, 45
DVDD
8
ODVDD
11
COUT
12
CDATA
14
CCLK
15
CLATCH
18
RESETB
19
SDATA_PA
20
BCLK_PA
21
LRCLK_PA
22
SDATA_PB
23
BCLK_PB
24
LRCLK_PB
25
DOUBLE
28, 32, 36
AGND
29
OUTA–
30
OUTA+
31, 33
AVDD
34
OUTB+
35
OUTB–
37
REFCAP
38
FILTCAP
Input/Output
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
IN
IN
Description
CLK27_PA clock (Pin 40) Divided by 1125
PLL_PB Clock (Pin 46) Divided by 512 (DOUBLE = 1) or 1024 (DOUBLE = 0)
CLK27_PB Clock (Pin 41) Divided by 1125
No Connection
Digital Ground
Digital Supply for DSP Core
Digital Supply for Output Buffers
SPI Readback
SPI Control Data Input
SPI Serial Bit Clock
SPI Control Latch Signal
Reset Signal for Both Processors, Active Low
Data Input to Processor A
Bit Clock Signal for Serial Data Input to Processor A
Left/Right Framing Signal for Data Input to Processor A
Data Input to Processor B
Bit Clock Signal for Serial Data Input to Processor B
Left/Right Framing Signal for Data Input to Processor B
Enables Internal Clock Doubler for 12.288 MHz Input (Both Processors)
Analog Ground
Negative Analog Output, Processor A
Positive Analog Output, Processor A
Analog Supply
Positive Analog Output, Processor B
Negative Analog Output, Processor B
Connection Point for 10 µF VREF Filter Capacitor
Connection for Noise Reduction Capacitor
Rev. 0 | Page 6 of 20
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