AD7150
500
250
0
–250
–500
1
10
100
RESISTANCE CIN TO GND (MΩ)
1000
Figure 10. Capacitance Input Offset Error vs. Resistance CIN to GND,
VDD = 3.3 V, EXC Pin Open Circuit
10
5
0
–5
–10
1
10
100
RESISTANCE CIN TO GND (MΩ)
1000
Figure 11. Capacitance Input Gain Error vs. Resistance CIN to GND,
VDD = 3.3 V, CIN to EXC = 2 pF
10
5
0
–5
–10
0
2
4
6
8
10
RESISTANCE EXC TO GND (MΩ)
Figure 12. Capacitance Input Offset Error vs. Resistance EXC to GND,
VDD = 3.3 V, CIN Pin Open Circuit
0.50
0.25
0
–0.25
–0.50
0
2
4
6
8
10
RESISTANCE EXC TO GND (MΩ)
Figure 13. Capacitance Input Gain Error vs. Resistance EXC to GND,
VDD = 3.3 V, CIN to EXC = 2 pF
2
0
–2
–4
–6
–8
0
50
100
150
200
250
SERIAL RESISTANCE (kΩ)
Figure 14. Capacitance Input Gain Error vs. Serial Resistance,
VDD = 3.3 V, CIN to EXC = 2 pF
10
5
0
–5
–10
1
10
100
PARALLEL RESISTANCE (MΩ)
1000
Figure 15. Capacitance Input Gain Error vs. Parallel Resistance,
VDD = 3.3 V, CIN to EXC = 2 pF
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