AD7151 View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
AD7151 Datasheet PDF : 28 Pages
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AD7151
Parameter
Min
Typ
Max
Unit 1
POWER REQUIREMENTS
VDD-to-GND Voltage
2.7
IDD Current4
70
IDD Current Power-Down Mode4
1
3.6
V
80
μA
5
μA
3
10
μA
Test Conditions/Comments
VDD = 3.3 V, nominal
Temperature ≤ 25°C
Temperature = 85°C
1 Capacitance units: one picofarad (1 pF) = 1 × 10−12 farad (F); one femtofarad (1 fF) = 10−15 farad (F).
2 The CAPDAC can be used to shift (offset) the input range. The total capacitance of the sensor can, therefore, be up to the sum of the CAPDAC value and the conversion
input range. With the autoCAPDAC feature, the CAPDAC is adjusted automatically when the CDC input value is lower than 25% or higher than 75% of the CDC
nominal input range.
3 Specification is not production tested but is supported by characterization data at initial product release.
4 Digital inputs equal to VDD or GND.
TIMING SPECIFICATIONS
VDD = 2.7 V to 3.6 V; GND = 0 V; Input Logic 0 = 0 V; Input Logic 1 = VDD; –40°C to +85°C, unless otherwise noted.
Table 2.
Parameter
CONVERTER
Conversion Time
Wake-Up Time from Power-Down Mode1, 2
Power-Up Time1, 3
Reset Time1, 4
SERIAL INTERFACE5, 6
SCL Frequency
SCL High Pulse Width, tHIGH
SCL Low Pulse Width, tLOW
SCL, SDA Rise Time, tR
SCL, SDA Fall Time, tF
Hold Time (Start Condition), tHD;STA
Setup Time (Start Condition), tSU;STA
Data Setup Time, tSU;DAT
Setup Time (Stop Condition), tSU;STO
Data Hold Time (Master), tHD;DAT
Bus-Free Time (Between Stop and Start Condition), tBUF
Min Typ Max
10
0.3
2
2
0
400
0.6
1.3
0.3
0.3
0.6
0.6
0.1
0.6
10
1.3
Unit
ms
ms
ms
ms
kHz
μs
μs
μs
μs
μs
μs
μs
μs
ns
μs
Test Conditions/Comments
See Figure 2.
After this period, the first clock is generated.
Relevant for repeated start condition.
1 Specification is not production tested but is supported by characterization data at initial product release.
2 Wake-up time is the maximum delay between the last SCL edge writing the configuration register and the start of conversion.
3 Power-up time is the maximum delay between the VDD crossing the minimum level (2.7 V) and either the start of conversion or when ready to receive a serial interface
command.
4 Reset time is the maximum delay between the last SCL edge writing the reset command and either the start of conversion or when ready to receive a serial interface
command.
5 Sample tested during initial release to ensure compliance.
6 All input signals are specified with input rise/fall times = 3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and outputs.
Output load = 10 pF.
tLOW tR
tF
tHD;STA
SCL
tHD;STA
tHD;DAT
tHIGH
tSU;DAT
tSU;STA
tSU;STO
SDA
tBUF
P
S
S
P
Figure 2. Serial Interface Timing Diagram
Rev. 0 | Page 4 of 28
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