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AD7153BRMZ View Datasheet(PDF) - Analog Devices

Part Name
Description
Manufacturer
AD7153BRMZ
ADI
Analog Devices ADI
AD7153BRMZ Datasheet PDF : 24 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
Data Sheet
AD7152/AD7153
SPECIFICATIONS
VDD = 2.7 V to 3.6 V; GND = 0 V; −40°C to +85°C, unless otherwise noted.
Table 1.
Parameter
CAPACITIVE INPUT
Capacitive Input Ranges
Gain Matching Between Ranges
Integral Nonlinearity (INL)2
No Missing Codes2
Resolution, p-p2, 3
Resolution Effective2, 3
Absolute Error4
Min Typ
Max Unit1
±2
pF
±1
pF
±0.5
pF
±0.25
pF
4
pF
2
pF
1
pF
0.5
pF
±3 % of FS
±0.05
% of FS
12
Bits
10
Bits
12
Bits
±20 fF
System Offset Calibration Range5, 6
Offset Deviation over Temperature2
40 % of FSR
1
5
fF
0.3
1
fF
Gain Error7
Gain Deviation over Temperature2
Allowed Capacitance, CIN to GND2
Allowed Resistance, CIN to GND2
Allowed Serial Resistance2
Power Supply Rejection DC
Normal-Mode Rejection2
Channel-to-Channel Isolation2
CAPDAC
Full Range
Resolution8
Differential Nonlinearity (DNL)2
Offset Deviation over Temperature2
EXCITATION
Frequency
Voltage
Allowed Capacitance, EXC to GND2
SERIAL INTERFACE LOGIC INPUTS (SCL, SDA)
Input High Voltage, VIH
Input Low Voltage, VIL
Input Leakage Current (SCL)
OPEN-DRAIN OUTPUT (SDA)
Output Low Voltage, VOL
Output High Leakage Current, IOH
POWER SUPPLY MONITOR
Threshold Voltage, VDD
0.5 % of FSR
0.3
0.4 % of FSR
50 pF
10 MΩ
20 kΩ
2
fF/V
−70
dB
−70
dB
−70
dB
5 6.25
pF
200
fF
0.25 LSB
0.3
% of CAPDAC FSR
30.9 32
32.8 kHz
±VDD/2
V
300 pF
1.5
±0.1
V
0.8 V
±5 µA
0.4 V
0.1
5
µA
2.45 2.65 V
Test Conditions/Comments
Differential mode
Single-ended mode
25°C, VDD = 3.3 V, 4 pF range
25°C, VDD = 3.3 V, 4 pF range
25°C, VDD = 3.3 V, after system offset
calibration, ±2 pF range
Single-ended mode, CIN and EXC
pins disconnected, see Figure 8
Differential mode, CIN and EXC
pins disconnected
25°C, VDD = 3.3 V
See Figure 7
See Figure 9 and Figure 10
See Figure 13
See Figure 16
See Figure 17
50 Hz ± 1 Hz, conversion time = 60 ms
60 Hz ± 1 Hz, conversion time = 50 ms
AD7152 only
5-bit CAPDAC
See Figure 18 and Figure 19
Single-ended mode
See Figure 11 and Figure 12
ISINK = 6.0 mA
VOUT = VDD
Rev. A | Page 3 of 24

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