AD7153 View Datasheet(PDF) - Analog Devices

Part Name

Description

Manufacturer

AD7153

12-Bit Capacitance-to-Digital Converter

Analog Devices 

Data Sheet

AD7152/AD7153

TIMING SPECIFICATIONS

VDD = 2.7 V to 3.6 V; GND = 0 V; Input Logic 0 = 0 V; Input Logic 1 = VDD; −40°C to +85°C, unless otherwise noted.

Table 2.

Parameter

SERIAL INTERFACE1, 2

SCL Frequency

SCL High Pulse Width, tHIGH

SCL Low Pulse Width, tLOW

SCL, SDA Rise Time, tR

SCL, SDA Fall Time, tF

Hold Time (Start Condition), tHD;STA

Set-Up Time (Start Condition), tSU;STA

Data Set-Up Time, tSU;DAT

Setup Time (Stop Condition), tSU;STO

Data Hold Time, tHD;DAT (Master)

Bus-Free Time (Between Stop and Start Conditions, tBUF)

Min Typ Max Unit Test Conditions/Comments

See Figure 3.

0

400 kHz

0.6

µs

1.3

µs

0.3 µs

0.3 µs

0.6

µs After this period, the first clock is generated.

0.6

µs Relevant for repeated start condition.

0.1

µs

0.6

µs

0.01

µs

1.3

µs

1 Sample tested during initial release to ensure compliance.

2 All input signals are specified with input rise/fall times = 3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and outputs;

output load = 10 pF.

SCL

tLOW tR

tHD;STA

tHD;DAT

SDA

tBUF

P

S

tF

tHIGH

tSU;DAT

tHD;STA

tSU;STA

S

Figure 3. Serial Interface Timing Diagram

tSU;STO

P

Rev. A | Page 5 of 24

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