AD7291(Rev0) View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
AD7291 Datasheet PDF : 28 Pages
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AD7291
I2C TIMING SPECIFICATIONS
Guaranteed by initial characterization. All values were measured with the input filtering enabled. CB refers to the capacitive load on the
bus line, with tR and tF measured between 0.3 × VDRIVE and 0.7 × VDRIVE (see Figure 2). VDD = 2.8 V to 3.6 V; VDRIVE = 1.65 V to 3.6 V; VREF =
2.5 V internal/external; TA = −40°C to +125°C, unless otherwise noted.
Table 3.
Parameter
fSCL
t1
t2
t3
t4 1
t5
t6
t7
t8
t9
t10
t11
t11A
t12
tSP
tPOWER-UP
Conditions
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Fast mode
Limit at TMIN, TMAX
Min
Typ Max
100
400
4
0.6
4.7
1.3
250
100
0
3.45
0
0.9
4.7
0.6
4
0.6
4.7
1.3
4
0.6
1000
20 + 0.1 CB
300
300
20 + 0.1 CB
300
1000
20 + 0.1 CB
300
1000
20 + 0.1 CB
300
300
20 + 0.1 CB
300
0
50
6
Unit Description
kHz Serial clock frequency
kHz
μs
tHIGH, SCL high time
μs
μs
tLOW, SCL low time
μs
ns
tSU;DAT, data setup time
ns
μs
tHD;DAT, data hold time
μs
μs
tSU;STA, setup time for a repeated start condition
μs
μs
tHD;STA, hold time for a repeated start condition
μs
μs
tBUF, bus-free time between a stop and a start condition
μs
μs
tSU;STO, setup time for a stop condition
μs
ns
tRDA, rise time of the SDA signal
ns
ns
tFDA, fall time of the SDA signal
ns
ns
tRCL, rise time of the SCL signal
ns
ns
tRCL1, rise time of the SCL signal after a repeated
ns
start condition and after an acknowledge bit
ns
tFCL, fall time of the SCL signal
ns
ns
Pulse width of the suppressed spike
ms Power-up and acquisition time
1 A device must provide a data hold time for SDA to bridge the undefined region of the SCL falling edge.
t11
t12
t2
t6
SCL
t6
t4
SDA
t7
P
S
S = START CONDITION
P = STOP CONDITION
t3
t1
t5
t10
S
t8
t9
P
Figure 2. 2-Wire Serial Interface Timing Diagram
Rev. 0 | Page 5 of 28
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