MXED102 View Datasheet(PDF) - Clare Inc => IXYS
Part Name
Description
Manufacturer
MXED102 Datasheet PDF : 20 Pages
| |||
MXED102
Preliminary
Registers 11 thru 63 - Undefined
Output Registers
Register Address 0 - Test Register
Register Address 1 - Status Register 0
Bit(s)
7-0
Name
Undefined
Description
-
Default
-
Register Address 2 - A/D Converter Output Register
Registers 3 thru 63 - Undefined
Power on Reset:
The part contains a power on reset circuit that ensures that the serial bus data registers come up in their default
value when VCC is cycled on. This brings up the part in its standby mode.
Digital Timing:
Parameter
Shift clock frequency
Shift clock minimum high
or low pulse width
Exposure clock frequency
Sym
-
-
-
Exposure clock minimum
high or low pulse width
Data and token setup/hold
time
Latch enable setup/hold time
Token bit output delay
Last data to latch enable time
Latch disable to new data time
-
tDSU , tTSU,
tDHD , tTHD
tLSU , tLHD
tTD
tDLD
tLDD
Operating Conditions
-
-
Control reg 2, bit 1 = 0
Control reg 2, bit 1 = 1
-
-
-
-
-
-
Min Typ Max Unit
-
-
25 MHz
16 -
- nS
1.0
-
10 MHz
-
- 1.0 MHz
80 -
- nS
10 -
- nS
40 -
-
-
200 -
10 -
- nS
15 nS
- nS
- nS
Precharge Voltage Generator:
Parameter
Precharge voltage generator
voltage and voltage error
Sym
VPRE
Precharge voltage generator
-
output impedance
Load capacitance
-
Operating Condition
VPRE = 30 * N / 256
for N = reg value,
0 < N < 256
4 < VPRE < VDD-4
-30 mA < IPRE < -50 mA
4 < VPRE < VDD-3
-5 mA < IPRE < -30 mA
5 < VPRE < VDD-4,
I = -15 mA
-
Min Typ Max Unit
-2 0
+2 %
-
-
TBD ohms
-
-
5 uF
8
www.clare.com
Rev. 2
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