AD9146(Rev0) View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
AD9146 Datasheet PDF : 52 Pages
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AD9146
DIGITAL SPECIFICATIONS
TMIN to TMAX, AVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IFS = 20 mA, maximum sample rate, unless otherwise noted.
Table 2.
Parameter
CMOS INPUT LOGIC LEVEL
Input VIN Logic High
Input VIN Logic Low
CMOS OUTPUT LOGIC LEVEL
Output VOUT Logic High
Output VOUT Logic Low
LVDS RECEIVER INPUTS1
Input Voltage Range, VIA or VIB
Input Differential Threshold, VIDTH
Input Differential Hysteresis, VIDTHH to VIDTHL
Receiver Differential Input Impedance, RIN
LVDS Input Rate
DAC CLOCK INPUT (DACCLKP, DACCLKN)
Differential Peak-to-Peak Voltage
Common-Mode Voltage
Maximum Clock Rate
REFCLK INPUT (REFCLKP, REFCLKN)
Differential Peak-to-Peak Voltage
Common-Mode Voltage
REFCLK Frequency
PLL Mode
SYNC Mode
SERIAL PORT INTERFACE
Maximum Clock Rate (SCLK)
Minimum Pulse Width High (tPWH)
Minimum Pulse Width Low (tPWL)
Setup Time, SDIO to SCLK (tDS)
Hold Time, SDIO to SCLK (tDH)
Data Valid, SDIO to SCLK (tDV)
Setup Time, CS to SCLK (tDCSB)
Test Conditions/Comments
Min
Typ
1.2
1.4
Applies to data, DCI, and FRAME inputs
825
−100
20
80
See Table 5
Self-biased input, ac-coupled
100
500
1.25
1200
100
500
1.25
1 GHz ≤ fVCO ≤ 2.1 GHz
See the Multichip Synchronization
section for conditions
15.625
0
40
2.09
0.844
2.904
2.38
Max
Unit
V
0.6
V
V
0.4
V
1575
mV
+100
mV
mV
120
Ω
2000
mV
V
MHz
2000
mV
V
525
MHz
525
MHz
MHz
12.5
ns
12.5
ns
ns
ns
ns
ns
1 LVDS receiver is compliant with the IEEE 1596 reduced range link, unless otherwise noted.
DIGITAL INPUT DATA TIMING SPECIFICATIONS
Table 3.
Parameter
LATENCY (DACCLK CYCLES)
1× Interpolation (With or Without Modulation)
2× Interpolation (With or Without Modulation)
4× Interpolation (With or Without Modulation)
Inverse Sinc
Value
64
135
292
20
Unit
Cycles
Cycles
Cycles
Cycles
Rev. 0 | Page 5 of 52
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