AD9411 View Datasheet(PDF) - Analog Devices
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AD9411 Datasheet PDF : 28 Pages
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AD9411
SWITCHING SPECIFICATIONS
AVDD = 3.3 V, DRVDD = 3.3 V, TMIN = –40°C, TMAX = +85°C, unless otherwise noted.
Table 4.
Parameter (Conditions)
Maximum Conversion Rate1
Minimum Conversion Rate1
CLK+ Pulse Width High (tEH)1
CLK+ Pulse Width Low (tEL)1
OUTPUT (LVDS Mode)
Valid Time (tV)
Propagation Delay (tPD)
Rise Time (tR) (20% to 80%)
Fall Time (tF) (20% to 80%)
DCO Propagation Delay (tCPD)
Data to DCO Skew (tPD–tCPD)
Latency
Aperture Delay (tA)
Aperture Uncertainty (Jitter, tJ)
Temp
Full
Full
Full
Full
Test
Level
VI
V
IV
IV
Full VI
Full VI
25°C V
25°C V
Full VI
Full IV
Full IV
25°C V
25°C V
AD9411-170
AD9411-200
Min
Typ
Max Min Typ
Max
170
200
40
40
2
12.5 2
12.5
2
12.5 2
12.5
2.0
2.0
3.2
4.3
3.2
4.3
0.5
0.5
0.5
0.5
1.8
2.7
3.8 1.8 2.7
3.8
0.2
0.5
0.8 0.2 0.5
0.8
14
14
1.2
1.2
0.25
0.25
Out-of-Range Recovery Time
25°C V
1
1
Unit
MSPS
MSPS
ns
ns
ns
ns
ns
ns
ns
ns
Cycles
ns
ps
rms
Cycles
1 All ac specifications tested by driving CLK+ and CLK– differentially.
EXPLANATION OF TEST LEVELS
I. 100% production tested.
II. 100% production tested at 25°C and sample tested at specified temperatures.
III. Sample tested only.
IV. Parameter is guaranteed by design and characterization testing.
V. Parameter is a typical value only.
VI. 100% production tested at 25°C; guaranteed by design and characterization testing for industrial temperature range; 100%
production tested at temperature extremes for military devices.
AIN
CLK+
CLK–
DATA OUT
DCO+
DCO–
N–1
N
N+1
tEL
tEH
1/fS
tPD
N–14
N–13
14 CYCLES
N
N+1
tCPD
Figure 2. LVDS Timing Diagram
Rev. A | Page 6 of 28
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