AD9549(RevPrA) View Datasheet(PDF) - Analog Devices

Part Name

Description

Manufacturer

AD9549
(Rev.:RevPrA)

Dual Input Network Clock Generator/Synchronizer

Analog Devices 

Preliminary Technical Data

AD9549

TABLE OF CONTENTS

Features ...............................................................................................1

Applications .......................................................................................1

General Description..........................................................................1

Sample Application Circuit..............................................................2

DC Specifications ..............................................................................5

AC Specifications ..............................................................................7

Typical Performance Characteristics ............................................13

Absolute Maximum Ratings ..........................................................17

ESD Caution ................................................................................17

Pin Configuration and Function Descriptions ...........................18

Input / Output Termination Recommendations.........................21

Theory of Operation .......................................................................22

Overview ......................................................................................22

PLL Core (DPLLC) .....................................................................23

Feedforward Divider (Divide-by-R).....................................23

Feedback Divider (Divide-by-S) ...........................................23

Forward and Reverse FEC Clock Scaling ............................24

Phase Detector.........................................................................24

Digital Loop Filter...................................................................24

Direct Digital Synthesizer ......................................................26

DAC Output.............................................................................27

Phase Detector.............................................................................27

Coarse Phase Detector ...........................................................27

Fine Phase Detector................................................................27

Phase Detector Gain Matching .............................................28

Phase Detector Pin Connections ..........................................28

Digital Loop Filter Coefficients ................................................28

Closed Loop Phase Offset..........................................................30

Lock Detection ............................................................................31

Phase Lock Detection.............................................................31

Frequency Lock Detection ....................................................32

Reference Monitors ....................................................................33

Loss of Reference ....................................................................33

Reference Frequency Monitor...............................................33

Reference Switchover .................................................................34

Use of Line Card Mode to Eliminate Runt Pulses..............35

Holdover ......................................................................................36

Holdover Control....................................................................36

Holdover & Reference Switchover State Machine..............36

Reference Recovery Timers...................................................37

Holdover Operation ...............................................................38

Holdover Sampler and Averager...........................................39

Output Frequency Range Control ............................................39

Reconstruction Filter..................................................................39

Use of Narrowband Filter for High Performance...............40

FDBK Inputs................................................................................41

Reference Inputs .........................................................................41

Reference Clock Receiver ......................................................41

SysClk Inputs...............................................................................42

Functional Description ..........................................................42

Bipolar Edge Detector ............................................................42

SysClk PLL Multiplier ............................................................42

External Loop Filter (SysClk PLL) .......................................43

Detail of SysClk Differential Inputs .....................................43

Harmonic Spur Reduction.........................................................45

Output Clock Drivers & 2x frequency Multiplier ..................46

Primary 1.8V Differential HSTL Driver..............................46

2x Frequency Multiplier.........................................................46

Rev. PrA | Page 3 of 78

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