AD9549(RevPrA) View Datasheet(PDF) - Analog Devices

Part Name

Description

Manufacturer

AD9549
(Rev.:RevPrA)

Dual Input Network Clock Generator/Synchronizer

Analog Devices 

AD9549

Single-Ended CMOS Output................................................ 46

Frequency Slew Limiter............................................................. 46

Frequency Estimator.................................................................. 47

Status and Warnings .................................................................. 48

Status Pins ............................................................................... 48

Reference Monitor Status ...................................................... 49

Default DDS Output Frequency on Power-Up .................. 49

Interrupt Request (IRQ)........................................................ 49

Power-On Reset.......................................................................... 51

AD9549 Power Up and Programming Sequence................... 51

Power Management........................................................................ 52

3.3V Supplies............................................................................... 52

1.8V Supplies............................................................................... 52

Serial Control Port.......................................................................... 53

Serial Control Port Pin Descriptions....................................... 53

Operation of Serial Control Port.............................................. 53

Framing a Communication Cycle with CSB ...................... 53

Communication Cycle—Instruction Plus Data ................. 53

Write......................................................................................... 53

Preliminary Technical Data

Read ......................................................................................... 54

The Instruction Word (16 Bits)................................................ 54

MSB/LSB First Transfers ........................................................... 54

I/O Register Map ............................................................................ 58

1 Types of Registers:................................................................ 65

I/O Register Description ............................................................... 66

Serial Port Configuration (0000 – 0005)............................. 66

Power Down and Reset ......................................................... 66

System Clock........................................................................... 67

Digital PLL Control and Dividers........................................ 68

Digital PLL Loop Filter.......................................................... 69

Free-Run (Single-Tone) Mode.............................................. 70

Reference Selector / Holdover .............................................. 70

Doubler and Output Drivers ................................................ 71

Monitor.................................................................................... 72

Calibration (User Accessible Trim) ..................................... 75

Harmonic Spur Reduction.................................................... 77

Outline Dimensions ....................................................................... 78

Ordering Guide............................................................................... 78

Rev. PrA | Page 4 of 78

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