AD9549(RevPrA) View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
AD9549 Datasheet PDF : 78 Pages
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AD9549
Preliminary Technical Data
SYSTEM CLOCK INPUT
SYSCLK PLL BYPASSED
Input Capacitance (DC)
Input Impedance (DC)
Common Mode Input Voltage3
Differential Input Voltage Swing3
Input Voltage High (VIH)
Input Voltage Low (VIL)
Input Current
SYSCLK PLL ENABLED
Input Capacitance (DC)
Input Impedance (DC)
Common Mode Input Voltage3
Differential Input Voltage Swing3
Input Voltage High (VIH)
Input Voltage Low (VIL)
Input Current
CRYSTAL RESONATOR WITH SYSCLK PLL ENABLED
Motional Resistance
CLOCK OUTPUT DRIVERS
HSTL OUTPUT DRIVER
Differential Output Voltage Swing4
1.5
1
3
2
TBD
700
Common Mode Output Voltage4
Continuous Output Current
CMOS OUTPUT DRIVER
Output Voltage High (VOH)
Output Voltage Low (VOL)
Output High Current (IOH)
Output Low Current (IOL)
TOTAL POWER DISSIPATION
All Blocks Running
Power-Down Mode
TBD
0.9
7.2
0.4
TBD
TBD
TBD
TBD
Default with SysClk PLL Enabled
TBD
TBD
Default with SysClk PLL Disabled
TBD
TBD
- with Digital Power Down
TBD
- with REFA or REFB Power Down
TBD
- with HSTL Clock Driver Power Down
TBD
- with CMOS Clock Driver Power Down
TBD
- with HSTL 2x Freq. Multiplier Power
TBD
Down
1 Must be ≤ 0V relative to AVDD3 (pin 14) and ≥ 0V relative to AVSS (pins 33, 43).
2 Must be ≤ 0V relative to AVDD (pin 42) and ≥ 0V relative to AVSS (pins 33, 43).
3 Relative to AVSS (pins 33, 43).
4 Must be ≤ 0V relative to AVDD (pin 36) and ≥ 0V relative to AVSS (pins 33, 43).
5 See “Power Management” Section for details about power profiles.
Rev. PrA | Page 6 of 78
pF
single-ended, each pin
KΩ differential
differential operation
differential operation
single-ended operation
single-ended operation
single-ended operation
pF
single-ended, each pin
KΩ differential
differential operation
differential operation
single-ended operation
single-ended operation
single-ended operation
kΩ
mV Both pins AC-coupled using 0.01uF,
then 50Ω to GND,
V
mA
V
V
µA
µA
mW TBD
mW Using either the Power Down
Register or PWRDOWN pin.
mW After reset or power up with fS=1GHz,
S4=0, S1-S3=1, fSYSCLK=25MHz
mW After reset or power up with fS=1GHz,
S4-S4=1, & Sysclk PLL powered down.
mW
mW One reference still powered up.
mW
mW
mW
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