AD9549 View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
AD9549 Datasheet PDF : 76 Pages
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AD9549
Parameter
CMOS Output Driver
(AVDD3/Pin 37) @ 3.3 V
Frequency Range
Duty Cycle
Rise Time/Fall Time (20-80%)
CMOS Output Driver
(AVDD3/Pin 37) @ 1.8 V
Frequency Range
Duty Cycle
Rise Time/Fall Time (20% to 80%)
HOLDOVER
Frequency Accuracy
OUTPUT FREQUENCY SLEW LIMITER
Slew Rate Resolution
Slew Rate Range
REFERENCE MONITORS
Loss of Reference Monitor
Operating Frequency Range
Minimum Frequency Error for
Continuous REF Present Indication
Minimum Frequency Error for
Continuous REF Present Indication
Maximum Frequency Error for
Continuous REF Lost Indication
Maximum Frequency Error for
Continuous REF Lost Indication
Reference Quality Monitor
Operating Frequency Range
Frequency Resolution (Normalized)
Frequency Resolution (Normalized)
Validation Timer
Timing Range
Timing Range
DAC OUTPUT CHARACTERISTICS
DCO Frequency Range (1st Nyquist Zone)
Output Resistance
Output Capacitance
Full-Scale Output Current
Gain Error
Output Offset
Voltage Compliance Range
DIGITAL PLL
Minimum Open-Loop Bandwidth
Maximum Open-Loop Bandwidth
Minimum Phase Margin
Maximum Phase Margin
PFD Input Frequency Range
Feedforward Divider Ratio
Feedback Divider Ratio
Min
Typ
0.008
45
55
3
0.008
45
55
5
0.54
0
7.63 × 103
−32
−35
0.008
0.2
408
32 × 10−9
65 × 10−6
10
50
5
20
−10
AVSS − +0.5
0.50
0.1
100
0
10
85
~0.008
1
1
Max
Unit
Test Conditions/Comments
150
MHz
See Figure 14 for maximum toggle rate
65
%
With 20 pF load and up to 150 MHz
4.6
ns
With 20 pF load
40
MHz
See Figure 13 for maximum toggle rate
65
%
With 20 pF load and up to 40 MHz
6.8
ns
With 20 pF load
See the Holdover section
111
3 × 1016
Hz/sec
Hz/sec
P = 216 for minimum; P = 25 for maximum
P = 216 for minimum; P = 25 for maximum
167 × 106 Hz
−16
ppm
−19
%
ppm
%
fREF = 8 kHz
fREF = 155 MHz
fREF = 8 kHz
fREF = 155 MHz
150
MHz
ppm
ppm
137
sec
2.8 × 105 sec
450
31.7
+10
0.6
AVSS +
0.50
MHz
Ω
pF
mA
% FS
μA
fREF = 8 kHz; OOL divider = 65,535 for minimum; OOL
divider = 1 for max (see the Reference Frequency
Monitor section)
fREF = 155 MHz; OOL divider = 65,535 for minimum;
OOL divider = 1 for maximum
See the Reference Validation Timers section
PIO = 5
PIO = 16
DPLL loop bandwidth sets lower limit
Single-ended (each pin internally terminated to AVSS)
Range depends on DAC RSET resistor
Outputs not dc-shorted to VSS
90
~24.5
131,070
131,070
Hz
kHz
Degrees
Degrees
MHz
Dependent on the frequency of REFA/REFB, the DAC
sample rate, and the P-, R-, and S-divider values
Dependent on the frequency of REFA/REFB, the DAC
sample rate, and the P-, R-, and S-divider values
Dependent on the frequency of REFA/REFB, the DAC
sample rate, and the P-, R-, and S-divider values
Dependent on the frequency of REFA/REFB, the DAC
sample rate, and the P-, R-, and S-divider values
1, 2, …, 65,535 or 2, 4, …, 131,070
1, 2, …, 65,535 or 2, 4, …, 131,070
Rev. D | Page 7 of 76
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