AD9549 View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
AD9549 Datasheet PDF : 76 Pages
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AD9549
Parameter
LOCK DETECTION
Phase Lock Detector
Time Threshold Programming Range
Time Threshold Resolution
Lock Time Programming Range
Unlock Time Programming Range
Frequency Lock Detector
Normalized Frequency Threshold
Programming Range
Normalized Frequency Threshold
Programming Resolution
Lock Time Programming Range
Unlock Time Programming Range
DIGITAL TIMING SPECIFICATIONS
Time Required to Enter Power-Down
Time Required to Leave Power-Down
Reset Assert to High-Z Time
for S1 to S4 Configuration Pins
Reset Deassert to Low-Z Time
for S1 to S4 Configuration Pins
SERIAL PORT TIMING SPECIFICATIONS
SCLK Clock Rate (1/tCLK )
Min
Typ Max
Unit
0
2097
μs
0.488
ps
32 × 10−9
275
sec
192 ×
10−9
67 × 10−3 sec
0
0.0021
32 × 10−9
192 ×
10−9
5×
10−13
275
sec
67 × 10−3 sec
15
µs
18
µs
60
ns
30
ns
25
50
MHz
SCLK Pulse Width High, tHIGH
8
SCLK Pulse Width Low, tLOW
8
SDO/SDIO to SCLK Setup Time, tDS
1.93
SDO/SDIO to SCLK Hold Time, tDH
1.9
SCLK Falling Edge to Valid Data on
SDIO/SDO, tDV
CSB to SCLK Setup Time, tS
1.34
CSB to SCLK Hold Time, tH
−0.4
CSB Minimum Pulse Width High, tPWH
3
IO_UPDATE Pin Setup Time
tCLK
from SCLK Rising Edge of the Final Bit
ns
ns
ns
ns
11
ns
ns
ns
ns
sec
IO_UPDATE Pin Hold Time
tCLK
sec
PROPAGATION DELAY
FDBK_IN to HSTL Output Driver
2.8
ns
FDBK_IN to HSTL Output Driver with 2×
7.3
ns
Frequency Multiplier Enabled
FDBK_IN to CMOS Output Driver
8.0
ns
FDBK_IN Through S-Divider to CMOS
Output Driver
8.6
ns
Frequency Tuning Word Update,
IO_UPDATE Pin Rising Edge to DAC
Output
60/fs
ns
Test Conditions/Comments
FPFD_gain = 200
FPFD_gain = 200
In power-of-2 steps
In power-of-2 steps
FPFD_gain = 200; normalized to (fREF/R)2; see the
Frequency Lock Detection section for details
FPFD_gain = 200; normalized to (fREF/R)2; see the
Frequency Lock Detection section for details
In power-of-2 steps
In power-of-2 steps
Time from rising edge of RESET to high-Z on the S1,
S2, S3, and S4 configuration pins
Time from falling edge of RESET to low-Z on the S1, S2,
S3, and S4 configuration pins
Refer to Figure 58 for all write-related serial port
parameters, maximum SCLK rate for readback is
governed by tDV
Refer to Figure 56
tCLK = period of SCLK in Hz
tCLK = period of SCLK in Hz
fs = system clock frequency in GHz
Rev. D | Page 8 of 76
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