AD9617AQ View Datasheet(PDF) - Analog Devices
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AD9617AQ Datasheet PDF : 10 Pages
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AD9617
THEORY OF OPERATION
The AD9617 has been designed to combine the key attributes of
traditional “low frequency” precision amplifiers with exceptional
high frequency characteristics that are independent of closed-
loop gain. Previous “high frequency” closed-loop amplifiers have
low open loop gain relative to precision amplifiers. This results
in relatively poor dc nonlinearity and precision, as well as exces-
sive high frequency distortion due to open loop gain roll-off.
Operational amplifiers use two basic types of feedback correc-
tion, each with advantages and disadvantages. Voltage feedback
topologies exhibit an essentially constant gain bandwidth prod-
uct. This forces the closed-loop bandwidth to vary inversely with
closed-loop gain. Moreover, this type design typically slew rate
limits in a way that causes the large signal bandwidth to be
much lower than its small signal characteristics.
A newer approach is to use current feedback to realize better
dynamic performance. This architecture provides two key at-
tributes over voltage feedback configurations: (1) avoids slew
rate limiting and therefore large signal bandwidth can approach
small signal performance; and (2) low bandwidth variation ver-
sus gain settings, due to the inherently low open loop inverting
input resistance (RS).
The AD9617 uses a new current feedback topology that over-
comes these limitations and combines the positive attributes of
both current feedback and voltage feedback designs. These
devices achieve excellent high frequency dynamics (slew, BW
and distortion) along with excellent low frequency linearity and
good dc precision.
DC GAIN CHARACTERISTICS
A simplified equivalent schematic is shown below. When operat-
ing the device in the inverting mode, the input signal error
current (IE) is amplified by the open loop transimpedance gain
(TO). The output signal generated is equal to TO × IE. Negative
feedback is applied through RF such that the device operates at a
gain (G) equal to –RF/RI.
Noninverting operation is similar, with the input signal applied
to the high impedance buffer (noninverting) input. As before, an
output (buffer) error current (IE) is generated at the low imped-
ance inverting input. The signal generated at the output is fed
back to the inverting input such that the external gain is (l + RF/
RI). The feedback mechanics are identical to the voltage feed-
back topology when exact equations are used.
The major difference lies in the front end architecture. A voltage
feedback amplifier has symmetrical high resistance (buffered)
inputs. A current feedback amplifier has a high noninverting
resistance (buffered) input and a low inverting (buffer output)
input resistance. The feedback mechanics can be easily devel-
oped using current feedback and transresistance open loop gain
T(s) to describe the I/O relationship. (See typical specification
chart.)
DC closed-loop gain for the AD9617 can be calculated using
the following equations:
G
=
VO
VI
≈
− RF
1+1
/ RI
/ LG
inverting
(1)
G = VO
VN
≈
1 + RF
1+1/
/ RI
LG
noninverting (2)
where
1
LG
≈
( ) RS RF + RS ʈ RI
T (s)(RS ʈ RI )
(3)
Because the noninverting input buffer is not ideal, input resis-
tance RS (at dc) is gain dependent and is typically higher for
noninverting operation than for inverting operation. RS will
approach the same value (Ϸ7 Ω) for both at input frequencies
above 50 MHz. Below the open loop corner frequency, the
noninverting RS can be approximated as:
( ) ( ) RS
noninverting
Ts
≈ 7+
AO
= 7 + TO
AO dc
(4)
where: AO = Open Loop Voltage Gain Ϸ G × 600
Inverting RS below the open loop corner frequency can be ap-
proximated as:
( ) ( ) RS
inverting
Ts
≈ 7+
AO
= 7 + TO
AO dc
(5)
where: AO = 40,000.
The AD9617 approaches this condition. With TO = 1 × 106 Ω,
RL = 500 Ω and RS = 25 Ω (dc), a gain error no greater than
0.05% typically results for G = –1 and 0.15% for G = –40.
Moreover, the architecture linearizes the open loop gain over its
operating voltage range and temperature resulting in ≥16 bits of
linearity.
VN
RI
VI
CI
+
LS
RS
IE
–
CC
TO
RF
Figure 13. Equivalent Circuit
REV. B
VO
–7–
RL = 100⍀
0%
–2
–1
0
1
2
VOUT – Volts
Figure 14. DC Nonlinearity vs. VOUT
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