AD9643(RevE) View Datasheet(PDF) - Analog Devices

Part Name

Description

Manufacturer

AD9643
(Rev.:RevE)

14-Bit, 170 MSPS/210 MSPS/250 MSPS, 1.8 V Dual Analog-to-Digital Converter (ADC)

Analog Devices 

AD9643

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

ADC DC Specifications ............................................................... 3

ADC AC Specifications ............................................................... 4

Digital Specifications ................................................................... 6

Switching Specifications .............................................................. 8

Timing Specifications .................................................................. 9

Absolute Maximum Ratings.......................................................... 11

Thermal Characteristics ............................................................ 11

ESD Caution................................................................................ 11

Pin Configurations and Function Descriptions ......................... 12

Typical Performance Characteristics ........................................... 16

Equivalent Circuits ......................................................................... 22

Theory of Operation ...................................................................... 23

ADC Architecture ...................................................................... 23

REVISION HISTORY

1/14—Rev. D to Rev. E

Changes to Figure 32...................................................................... 29

2/13—Rev. C to Rev. D

Added tSSYNC and tHSYNC Minimum Parameters of 1 ns, Table 5 .. 9

1/13—Rev. B to Rev. C

Changes to Features Section............................................................ 1

Changes to Input Referred Noise Parameter, Table 1 .................. 3

Changes to Table 2............................................................................ 4

Change to Table 3 ............................................................................. 6

Changes to Table 4............................................................................ 8

Changes to Figure 5 ........................................................................ 14

Changes to Figure 29...................................................................... 19

Changes to Figure 30...................................................................... 20

Change to Reading the Memory Map Register Table Section....... 31

Changes to Table 14........................................................................ 33

Change to Memory Map Register Description Section............. 34

Updated Outline Dimensions ....................................................... 36

Data Sheet

Analog Input Considerations ................................................... 23

Voltage Reference ....................................................................... 25

Clock Input Considerations...................................................... 25

Power Dissipation and Standby Mode .................................... 26

Digital Outputs ........................................................................... 27

ADC Overrange (OR)................................................................ 27

Channel/Chip Synchronization.................................................... 28

Serial Port Interface (SPI).............................................................. 29

Configuration Using the SPI..................................................... 29

Hardware Interface..................................................................... 29

SPI Accessible Features.............................................................. 30

Memory Map .................................................................................. 31

Reading the Memory Map Register Table............................... 31

Memory Map Register Table..................................................... 32

Memory Map Register Description ......................................... 34

Applications Information .............................................................. 35

Design Guidelines ...................................................................... 35

Outline Dimensions ....................................................................... 36

Ordering Guide .......................................................................... 36

9/11—Rev. A to Rev. B

Changes to Table 1.............................................................................3

Changes to Table 2, ...........................................................................4

Changes to Table 3.............................................................................6

Changes to Table 4.............................................................................8

Changes to Table 8.......................................................................... 12

Changes to Table 9.......................................................................... 14

Changes to Typical Performance Characterisitics Section ....... 16

Added ADC Overrange (OR) Section......................................... 27

Changes to Channel/Chip Synchronization Section ................. 28

Changes to Reading the Memory Map Register Table

Section.............................................................................................. 31

Changes to Table 14 ....................................................................... 32

Changes to Memory Map Resgister Description Section ......... 34

5/11—Rev. 0 to Rev. A

Changes to Table 2, Worst Other (Harmonic or Spur)

Max Values .........................................................................................4

4/11—Revision 0: Initial Version

Rev. E | Page 2 of 36

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