AD9629 View Datasheet(PDF) - Analog Devices

Part Name

Description

Manufacturer

AD9629

12-Bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS, 1.8 V Analog-to-Digital Converter

Analog Devices 

AD9629

TIMING SPECIFICATIONS

Table 5.

Parameter

SPI TIMING REQUIREMENTS

tDS

tDH

tCLK

tS

tH

tHIGH

tLOW

tEN_SDIO

tDIS_SDIO

Conditions

Min

Setup time between the data and the rising edge of SCLK

2

Hold time between the data and the rising edge of SCLK

2

Period of the SCLK

40

Setup time between CSB and SCLK

2

Hold time between CSB and SCLK

2

SCLK pulse width high

10

SCLK pulse width low

10

Time required for the SDIO pin to switch from an input to an

10

output relative to the SCLK falling edge

Time required for the SDIO pin to switch from an output to an

10

input relative to the SCLK rising edge

Data Sheet

Typ

Max Unit

ns

ns

ns

ns

ns

ns

ns

ns

ns

Rev. B | Page 8 of 32

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